參數(shù)資料
型號: HC05JB4GRS
英文描述: 68HC(7)05JB4 General Release Specification
中文描述: 68HC(7)05JB4總發(fā)行規(guī)格
文件頁數(shù): 22/106頁
文件大?。?/td> 1366K
代理商: HC05JB4GRS
GENERAL RELEASE SPECIFICATION
July 16, 1999
MOTOROLA
2-4
MEMORY
MC68HC05J5A
REV 2.1
ADDR
REGISTER
Port A Pull-down/up
PDURA
Port B Pull-down/up
PDURB
Timer1 Control
T1CR
Timer1 Status
T1SR
Input Capture High
ICH
Input Capture Low
ICL
R/W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
R
W
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
$0010
PURA7
PURA6
PDRA5
PDRA4
PDRA3
PDRA2
PDRA1
PDRA0
$0011
PDRB5
PDRB4
0
PDRB3
0
PURB2
0
PURB1
PDRB0
0
$0012
ICIE
0
T1OIE
IEDGE
$0013
ICF
0
T1OF
0
0
0
0
0
$0014
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
$0015
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
$0016
Unimplemented
$0017
Unimplemented
$0018
Timer1 Counter High
TCNTH
Timer1 Counter Low
TCNTL
Alt. Counter High
ACNTH
Alt. Counter Low
ACNTL
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
$0019
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
$001A
BIT15
BIT14
BIT13
BIT12
BIT11
BIT10
BIT9
BIT8
$001B
BIT7
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
$001C
Unimplemented
$001D
Unimplemented
$001E
Reserved
R
R
R
R
R
R
R
R
$001F
Reserved
R
R
R
R
R
R
R
R
unimplemented bits
reserved bits
R
Figure 2-4. I/O Registers $0010-$001F
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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