參數(shù)資料
型號(hào)： HC05JB4GRS
英文描述： 68HC(7)05JB4 General Release Specification
中文描述： 68HC（7）05JB4總發(fā)行規(guī)格
文件頁(yè)數(shù)： 99/106頁(yè)
文件大小： 1366K
代理商： HC05JB4GRS
July 16, 1999
GENERAL RELEASE SPECIFICATION
MC68HC05J5A
REV 2.1
MOTOROLA
B-7
Supply Current
RUN
3
WAIT
4
STOP
5
LVR on
LVR off
I
DD
—
—
—
—
6
2
40
10
10
4
80
30
mA
mA
μ
A
μ
A
I/O Ports Hi-Z Leakage Current
PA0-7, PB0-5
(without individual pull-down/up activated)
I
Z
—
—
±
10
μ
A
Input Pull-down Current
PA0-5, PB0, PB3-5
(with individual pull-down activated)
I
IL
50
100
200
μ
A
Input Pull-up Current
RESET
—
–50
–100
–200
μ
A
Input Current
IRQ, OSC1
I
in
—
—
±1
μ
A
Capacitance
Ports (as Input or Output)
RESET, IRQ, OSC1, OSC2/R
C
out
C
in
—
—
—
—
12
8
pF
pF
Crystal/Ceramic Resonator Oscillator Mode
Internal Resistor
OSC1 to OSC2/R
R
OSC
—
2
—
M
Pull-up Resistor
PA6, PA7
6
PB1, PB2
R
PULLUP
2
10
5
30
10
60
K
K
LVR Trigger Voltage
V
LVRI
2.7
3.0
—
V
TCAP Input Threshold Voltage
1. V
DD
= 5.0Vdc ±10%, V
SS
= 0 Vdc, T
A
= –40
°
C to +85
°
C, unless otherwise noted.
2. Typical values reflect average measurements at midpoint of voltage range, 25
°
C only.
3. Run (Operating) I
, Wait I
: Measured using external square wave clock source to OSC1 (f
OSC
= 2.0 MHz), all
inputs 0.2 Vdc from rail; no DC loads, less than 50pF on all outputs, C
L
= 20 pF on OSC2/R.
4. Wait I
DD
: Only MFT and Timer1 active.
Wait I
DD
is affected linearly by the OSC2/R capacitance.
5. Stop I
DD
measured with OSC1 = V
SS
.
6. Input voltage level on PA6 or PA7 higher than 2.4V is guaranteed to be recognized as logical one and as logic
zero if lower than 0.8V. PA6 and PA7 pull-up resistor values are specified under the condition that pin voltage
ranges from 0V to 2.4V.
V
TCAP
—
V
DD
/2
—
V
Table B-3. DC Electrical Characteristics, V
DD
=5V
Characteristic
1
Symbol
Min
Typ
2
Max
Unit
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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