參數(shù)資料
型號: HM5425801BTT-75B
廠商: ELPIDA MEMORY INC
元件分類: DRAM
英文描述: 256M SSTL_2 interface DDR SDRAM 143 MHz/133 MHz/125 MHz/100 MHz 4-Mword 】 16-bit 】 4-bank/8-Mword 】 8-bit 】 4-bank/ 16-Mword 】 4-bit 】 4-bank
中文描述: 32M X 8 DDR DRAM, 0.75 ns, PDSO66
封裝: 0.400 INCH, PLASTIC, TSOP2-66
文件頁數(shù): 48/65頁
文件大小: 489K
代理商: HM5425801BTT-75B
HM5425161B, HM5425801B, HM5425401B Series
Data Sheet E0086H20
48
ICC Measurement Condition
Parameter
Symbol
Condition
Operating current
(ACTV-PRE)
I
CC0
One Bank ; CKE
V
(min), t
= t
(min); t
= t
(min);
DQ, DM and DQS inputs changing twice per clock cycle; address
and control inputs changing once per clock cycle
Operating current
(ACTV-READ-PRE)
I
CC1
One Bank; CKE
V
(min); Burst = 2; t
= t
(min); CL = 2.5; t
= t
(min); Iout = 0 mA; address and control inputs changing once
per clock cycle
Idle power down standby
current
I
CC2P
All banks idle; power down mode; CKE
V
IL
(max); t
CK
= t
CK
(min).
Vin = V
REF
for DQ, DQS and DM
All banks idle;
CS
V
(min); CKE
V
(min); t
= t
(min);
Address and other control inputs changing once per clock cycle.
Vin
V
IH
(min) or Vin
V
IL
(max) for DQ, DQS and DM.
One bank active; power down mode; CKE
V
IL
(max); t
CK
= t
CK
(min)
One bank; Active Precharge;
CS
V
(min); CKE
V
(min); t
=
t
(max); t
= t
(min); DQ,DM and DQS inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
Idle standby current
I
CC2N
Active power down standby
current
I
CC3P
Active standby current
I
CC3N
Operating current
(Burst read operation)
I
CC4R
One bank active ; CKE
V
(min); Burst = 2; Reads; Continuous
burst; address and control inputs changing once per clock cycle;
CL = 2.5; t
CK
= t
CK
(min); Iout = 0 mA;
One bank active; CKE
V
(min); Burst = 2; Writes; Continuous
burst; address and control inputs changing once per clock cycle;
CL = 2.5; t
= t
CK
(min); DQ, DM and DQS inputs changing twice
per clock cycle
Operating current
(Burst write operation)
I
CC4W
Auto refresh current
I
CC5
I
CC6
I
CC7A
t
RC
= t
RFC
(min); Vin
V
IL
(max) or
V
IH
(min)
CKE
0.2 V, Vin
0.2V or
V
CCQ
0.2V
4 banks active read with activate every 2 clocks, AP (Auto
Precharge) read every 2 clocks, BL = 4, t
=3, Iout = 0 mA,
100% DQ, DM and DQS inputs changing twice per clock cycle;
100% addresses changing once per clock cycle.
Self refresh current
Random read current
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