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參數(shù)資料
| 型號(hào)： | HPC |
| 文件頁數(shù)： | 4/30頁 |
| 文件大?。?/td> | 361K |
| 代理商： | HPC |
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Signal Descriptions
(Continued)
Signal
Reset
Active
Type
Load
Factor
Description
CPU CONTROL SIGNALS
ST1
ST2
RDY
NHLD
0
0
O
O
I
I
Bus Cycle Status: indicates first opcode fetch.
Bus Cycle Status: indicates machine states (skip, interrupt or instruction start).
Ready acknowledge. Used to extend the bus cycle for slower memories.
HOLD request, TRI-STATE Port A for external control of address/data bus.
Internal bus placed in precharge state.
Acknowledge of HOLD request.
All memory locations requiring wait states should be decoded and input on this
pin.
Select bit to indicate 8-bit or 16-bit mode. 16-bit-pull low. 8-bit-memory locations
external to core must be decoded on this pin.
Halt/Idle mode acknowledge. Indicates clock is halted at C1
e
0 and C2
e
1 for
Halt mode.
H
L
1
1
NHDA
WATA
I
L
H
O
I
1
SEL8
I
1
HALT
0
H
O
ADDRESS DECODE SIGNALS
SELA
SELB
SELC
SELD
SELX
SROM
SLIO
0
0
0
0
0
0
0
H
H
H
H
H
H
H
O
O
O
O
O
O
O
Decode output indicating user peripheral address block 0100–011F.
Decode output indicating user peripheral address block 0120–013F.
Decode output indicating user peripheral address block 0140–015F.
Decode output indicating user peripheral address block 0160–017F.
Decode output indicating user peripheral address block 0200–EFFF.
Decode output indicating user peripheral address block F000–FFFF.
Decode output indicating user peripheral address block 00E0–00FF.
TEST SIGNALS
*
TEST
TST1
TST2
TRST
TCLK
MUX(0:8)
USR(0:8)I
H
I
I
I
I
I
12
2
1
1
1
Selects test mode.
Input for RDY/HOLD signals in test mode. Not used in non test mode.
Input for T2IN/T3IN signals in test mode. Not used in non test mode.
Input for RSET signal in test mode. Not used in non test mode.
Input for clock signal in test mode. Not used in non test mode.
Output of test multiplexers. User outputs when not in test mode.
User logic inputs to output test multiplexers. Use to access test I/O pins in user
logic mode.
H
O
*
All test signals must be brought to an appropriate I/O macro.
Z
e
Tristate
U
e
Unknown
H
e
Active High
L
e
Active Low
I
e
Input
B
e
Bidirectional
O
e
Output
HPC Core DC Characteristics
V
CC
e
5.0V
g
10%
Symbol
Parameter
Test Conditions
Min
Typ
Max
Units
I
CC1
Active Current
V
CC
e
5.0V fc
e
17.0 MHz
30
mA
V
CC
e
5.0V fc
e
2.0 MHz
3.5
mA
I
CC2
Idle Mode Current
V
CC
e
5.0V fc
e
17.0 MHz
3.0
mA
V
CC
e
5.0V fc
e
2.0 MHz
0.35
mA
I
CC3
Halt Mode Current
V
CC
e
5.0V fc
e
0 kHz
200
m
A
V
CC
e
2.5V fc
e
0 kHz
100
m
A
V
RAM
RAM Keep Alive Voltage
2.5
V
C
BUS
Address/Data Bus Capacitive Load (DB(0:15))
pF
4
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