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參數(shù)資料
| 型號： | HPC |
| 文件頁數(shù)： | 3/30頁 |
| 文件大?。?/td> | 361K |
| 代理商： | HPC |
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Signal Descriptions
(Continued)
Signal
Reset
Active
Type
Load
Factor
Description
INTERRUPT SIGNALS
The core contains eight external interrupts.
I1–I4
INT5
I
I
1
1
Refer to Port I.
Interrupt: Enabled if bit 5 of ENIR is set. Level interrupt ORed with internal Timer
interrupt signals.
IRPD: Bit 5 is set when interrupt pending.
Interrupt: Enabled if bit 6 of ENIR is set. Level interrupt.
IRPD: Bit 6 is set when interrupt pending.
Interrupt: Enabled if bit 7 of ENIR is set. Level interrupt.
IRPD: Bit 7 is set when interrupt pending.
Core reset, level sensitive.
H
INT6
H
I
1
INT7
H
I
1
RSET
H
I
1
CLOCK SIGNALS
CKIN
C1
C2
NSTP
I
1
System clock. Typically connected to the output of an oscillator macro.
Buffered system clock, CKIN.
Buffered CKIN divided by 2.
Signal to stop an oscillator during halt mode.
O
O
O
1
L
WATCHDOG SIGNALS
WDOT
WDIN
STWD
0
H
L
H
O
I
I
Signal indicating an illegal condition has been detected by the watchdog logic.
Signal to reset watchdog logic.
Signal to force watchdog to trip.
1
1
MICROWIRE/PLUS SIGNALS
MWOT
U
O
m
WIRE output: serial output from SIO register bit 7.
m
CODE serial dump: serial output from
m
CODE shift register. This output is
multiplexed with the
m
WIRE output.
MWIN:
m
Wire input shared by Port I.
m
WIRE/PLUS clock input.
m
WIRE/PLUS clock output, tristable.
m
WIRE Master/Slave mode status. 1
e
Master
I5
OSKI
OSKO
MWMS
I
I
1
1
1
Z
0
O
O
0
e
Slave
TIMER SIGNALS
T2IN
T3IN
T2OT
I
I
1
1
Timer T2 external clock input (edge-triggered).
Timer T3 external clock input (edge-triggered).
Timer T2 output pulse (1 C1 wide) flagging underflow condition and triggering
reload of T2 with the data from R2.
Timer T3 output pulse (1 C1 wide) flagging underflow condition and triggering
reload of T3 with the data from R3.
General purpose programmable clock. Time base is selected through the DIVBY
register.
T0 carry output indicating T0 overflow condition. (1 C2 wide pulse.)
U
H
O
T3OT
U
H
O
TDIV
U
O
T0CY
I
H
O
ADDRESS/DATA BUS CONTROL SIGNALS
DB(0:15)
NRD
MTB
NWR
ALE
HBE
1/0
1
0
1
B
O
O
O
O
O
Internal 16-bit precharged address/data bus.
Read. Useable with internal address/data bus or port A.
Memory to Bus. Useable with internal address/data bus, only.
Write. Useable with internal address/data bus and Port A.
Address latch enable.
High byte enable.
L
H
L
H
H
0
Z
e
Tristate
H
e
Active High
U
e
Unknown
L
e
Active Low
I
e
Input
B
e
Bidirectional
O
e
Output
3
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