![](http://datasheet.mmic.net.cn/290000/HPC_datasheet_16135676/HPC_6.png)
HPC Core AC Timing Parameters
V
CC
e
5.0V
g
10% (Continued)
Symbol
Description
Min
**
Typ
**
Max
**
Units
READ CYCLE TIMINGDFigures 3 and 4
fc
e
17 MHz One Wait State
tDBAv
e
(/4
tC2–6
Databus Address Valid to ALE Trailing Edge
24
ns
tDBAiv
e
(/4
tC2–5
ALE Trailing Edge to Databus Address Invalid
24
ns
tACCI
e
tC2
a
WS
b
15
Address Valid to Input Data ValidDData Bus
221
ns
tDBDh
Data Bus Data In Hold to MTB Inactive
0
ns
tAMTB
e
(/4
tC2
b
10
ALE Trailing Edge to MTB Active
20
ns
tPAAV
e
(/4
tC2
b
12
Port A Address Valid to ALE Trailing Edge
18
ns
tPAAiv
e
(/4
tC2
b
10
ALE Trailing Edge to Port A Address Invalid
20
ns
tACCE
e
tC2
a
WS
e
55
Address Valid to Input Data ValidDPort A
181
ns
tPADs
Port A Data Setup to NRD Inactive
50
ns
tPADh
Port A Data Hold to NRD Inactive
0
ns
tANRD
e
(/4
tCD2
b
5
ALE Trailing Edge to NRD Active
24
ns
tNRDDv
e
(/2
tC2
a
WS
b
65
NRD Active to Port A Data Valid
112
ns
tNRDp
e
(/2
tC2
a
WS
b
10
NRD Pulse Width
167
ns
Symbol
Description
Ref
Best Case
*
Worst Case
*
Units
FO
e
1
d/FO
FO
e
1
d/FO
WRITE CYCLE TIMINGDFigure 5
tNWRa
Write Active
C1, RE
2.3
0.2
14.6
1.1
ns
tNWRia
Write Inactive
C2, RE
3.3
0.2
17.5
1.1
ns
Symbol
Description
Min
**
Typ
**
Max
**
Units
WRITE CYCLE TIMINGDFigures 6 and7
fc
e
17 MHz One Wait State
tDBDV
e
(/2
tC2
a
WS
b
15
Data Bus Data Out to NWR Inactive
165
ns
tDBDiv
NWR Inactive to Data Bus Data Out Invalid
0
ns
tPADv
e
(/2
tC2
a
WS
b
20
Port A Data Out to NWR Inactive
157
ns
tPADiv
e
(/4
tC2
b
10
NWR Inactive to Port A Data Out Invalid
20
ns
tANWR
e
(/2
TC2
b
5
**
Typical times for signal relationship information, only. Actual numbers depend on actual design loading of the signals involved. Parameters referencing Port A
include 4 mA I/O buffer on Port A and the delay of control signals brought through I/O buffers to pads.
ALE Trailing Edge to NWR Active
54
ns
Symbol
Description
Ref
Best Case
*
Worst Case
*
Units
FO
e
1
d/FO
FO
e
1
d/FO
READY MODEDFigure 8
tRDYs
e
40 ns
Ready Request Setup Time
C2, RE
tRDYh
e
50 ns
Ready Request Hold Time
C2, RE
HALT/IDLE MODEDFigure 9
tHALT
HALT/IDLE Request Acknowledge (Note 1)
C2, RE
6.4
0.8
31.1
4.3
ns
tNSTP
Stop Oscillator for HALT (Note 1)
C2, RE
5.6
0.4
26.6
2.4
ns
tNSTPia
Restart Oscillator in HALT (Note 1)
NMI, FE
5.6
0.4
26.6
2.4
ns
6