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參數(shù)資料
| 型號： | HPC |
| 文件頁數(shù)： | 18/30頁 |
| 文件大?。?/td> | 361K |
| 代理商： | HPC |
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16-Bit Address/Data Bus
Access to the internal 16-bit address/data bus provides un-
limited flexibility. A number of peripherals may be designed
to communicate with the bus. To increase the architecture
speed, the bus is precharged.
A precharged bus is different from a TRI-STATE bus. The
unselected state is a ‘‘1’’ rather than a ‘‘Z’’. When not se-
lected, the peripheral bit will remain high from the internal
precharge circuitry. The same holds true when a high level
is requested on the bit. Hence, response time is faster. A
low level is placed on the bus when the internal transistor is
pulled low. Bus precharge occurs when both clocks C1 and
C2 are in a high state. To avoid excessive loading on the
address/data bus, special macros have been created for
bus interfacing. A bus receiver or bus driver macro, avail-
able in the cell library should be used.
Figure 13 demonstrates how a peripheral may be connect-
ed to the precharge bus. The peripheral contains registers
located in the SELA address block of the memory map. The
bus LSBs are monitored through receiver macros and de-
coded to determine which unique address locations will re-
ceive data. Peripheral registers access the data bus through
a bus driver macro. Proper timing for communication with
the pre-charged bus is controlled with this macro through
the MTB and C2 timing signals during a read cycle. During a
write cycle, data is transferred from the bus to the peripheral
via the bus receiver macros and the NWR signal.
Wait States
The HPC core provides four software selectable Wait States
that allow access to slower memories. The Wait States are
selected by the state of two bits, Wait1 and Wait0, in the
PSW register. Table I indicates the number of programmed
wait states. Additionally, the RDY input may be used to ex-
tend the instruction cycle, allowing the user to interface with
slow memories and peripherals. Hardware decode of the
memory map address locations affected by wait states
should be provided on the WATA input.
TABLE I
Bit
Bit
Wait
States
Wait1
Wait0
0
0
1
1
0
1
0
1
4
2
1
0
Power Save Modes
Two power saving modes are available on the HPC core:
HALT and IDLE. In the HALT mode, all processor activities
are stopped. In the IDLE mode, the on-board oscillator and
timer T0 are active but all other processor activities are
stopped. In either mode, all on-board RAM, registers and
I/O are unaffected.
HALT Mode
The HPC core is placed in the HALT mode under software
control by setting bits in the PSW register. All processor
activities, including the clock and timers, are stopped. The
stop clock (NSTP) output is gated with the clock input (CKI)
signal to inhibit clock oscillation at the core input when a
clock I/O oscillator macro is used. The HALT output goes
high designating that the core is in HALT mode. In this
mode, power requirements for the HPC are minimal and the
applied voltage (V
CC
) may be decreased without altering the
state of the machine. V
CC
may be decreased as low as the
RAM keep alive voltage.
There are two ways of exiting the HALT mode: via the RSET
or NMI interrupts. The RSET input reinitializes the proces-
sor. Exiting with an NMI input will generate a vectored inter-
rupt. Operation will resume from that point with no initializa-
tion. The HALT mode can be enabled or disabled by means
of a control register HALT enable. To prevent accidental
use of the HALT mode the HALT enable register can be
modified only once.
TL/U/9982–27
FIGURE 13. Peripheral Connections on the Address/Data Bus
18
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