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參數(shù)資料
| 型號： | HYB18T256160AF-3 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 256 Mbi t DDR2 SDRAM |
| 中文描述： | 256姆噸DDR2內(nèi)存 |
| 文件頁數(shù)： | 29/90頁 |
| 文件大小： | 1246K |
| 代理商： | HYB18T256160AF-3 |
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HYB18T256400/800/160AF
256Mb DDR2 SDRAM
INFINEON Technologies
Page 29 Rev. 1.02 May 2004
2.6 Read and Write Commands and Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS high,
CS and CAS low at the clock’s rising edge. WE must also be defined at this time to determine whether the access
cycle is a read operation (WE high) or a write operation (WE low). The DDR2 SDRAM provides a wide variety of
fast access modes. A single Read or Write Command will initiate a serial read or write operation on successive
clock cycles at data rates of up to 667Mb/sec/pin for main memory. The boundary of the burst cycle is restricted to
specific segments of the page length.
For example, the 16Mbit x 4 I/O x 4 Bank chip has a page length of 2048 bits (defined by CA0-CA9 & CA11).
In case of a 4-bit burst operation (burst length = 4) the page length of 2048 is divided into 512 uniquely address-
able segments (4-bits x 4 I/O each). The 4-bit burst operation will occur entirely within one of the 512 segments
(defined by CA0-CA8) beginning with the column address supplied to the device during the Read or Write Com-
mand (CA0-CA9 & A11). The second, third and fourth access will also occur within this segment, however, the
burst order is a function of the starting address, and the burst sequence.
In case of a 8-bit burst operation (burst length = 8) the page length of 2048 is divided into 256 uniquely address-
able double segments (8-bits x 4 I/O each). The 8-bit burst operation will occur entirely within one of the 256 dou-
ble segments (defined by CA0-CA7) beginning with the column address supplied to the device during the Read or
Write Command (CA0-CA9 & CA11).
A new burst access must not interrupt the previous 4 bit burst operation in case of BL = 4 setting. Therefore the
minimum CAS to CAS delay (tCCD) is a minimum of 2 clocks for read or write cycles
.
For 8 bit burst operation (BL = 8) the minimum CAS to CAS delay (tCCD) is 4 clocks for read or write cycles.
Burst interruption is allowed with 8 bit burst operation. For details see the “Burst Interrupt” - Section of this
datasheet.
Example:
Read Burst Timing Example: (CL = 3, AL = 0, RL = 3, BL = 4)
NOP
NOP
NOP
NOP
NOP
READ A
T0
T2
T1
T3
T4
T5
T6
T7
T12
CMD
DQ
RB
DQS,
DQS
READ B
NOP
Dout A0
Dout A1
Dout A2
Dout A3 Dout B0
Dout B1
Dout B2
Dout B3
Dout C0
Dout C1
Dout C2
Dout C3
NOP
READ C
tCCD
tCCD
CK, CK
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相關(guān)代理商/技術(shù)參數(shù) |
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| HYB18T256400AF-3.7 | 制造商:Infineon Technologies AG 功能描述:64M X 4 DDR DRAM, 0.5 ns, PBGA60 |
| HYB18T256400AF-5 | 制造商:Infineon Technologies AG 功能描述:SDRAM, DDR, 64M x 4, 60 Pin, Plastic, BGA |
| HYB18T256800AF-5 | 制造商:Infineon Technologies AG 功能描述: |
| HYB18T512161BF-25 | 制造商:Qimonda 功能描述:SDRAM, DDR, 32M x 16, 84 Pin, Plastic, BGA |
| HYB18T512400AF-5 | 制造商:Intersil Corporation 功能描述:SDRAM, DDR, 128M x 4, 60 Pin, Plastic, BGA |
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