參數(shù)資料
型號(hào)： HYB18T256160AF-3
廠商： INFINEON TECHNOLOGIES AG
英文描述： 256 Mbi t DDR2 SDRAM
中文描述： 256姆噸DDR2內(nèi)存
文件頁(yè)數(shù)： 57/90頁(yè)
文件大小： 1246K
代理商： HYB18T256160AF-3
HYB18T256400/800/160AF
256Mb DDR2 SDRAM
INFINEON Technologies
Page 57 Rev. 1.02 May 2004
Active Power-Down Mode Entry and Exit after a Write Command: WL = 2, tWTR = 2, BL = 4
Active Power-Down Mode Entry and Exit after a Write Command with AP: WL = 2, tWR = 3, BL = 4
note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12.
NOP
NOP
W RITE
T0
T2
T1
T3
T4
T5
T6
T7
CMD
DQ
DQS,
DQS
NOP
NOP
NOP
NOP
NOP
NOP
Tn
Tn+1
CKE
WL = RL - 1 = 2
WL + BL/2 + tWTR
NOP
NOP
Act.PD 2
tWTR
tIS
Tn+2
tIS
Valid
Command
Active
Power-Down
Exit
tXARD or
tXARDS *)
CK, CK
DIN A0 DIN A1 DIN A2 DIN A3
Active
Power-Down
Entry
note: Active Power-Down mode exit timing tXARD (“fast exit”) or tXARDS (“slow exit”) depends on the programmed
state in the MRS, address bit A12.WR is the programmed value in the MRS mode register.
NOP
NOP
W RITE
w/AP
T0
T2
T1
T3
T4
T5
T6
T7
CMD
DQ
DQS,
DQS
NOP
NOP
NOP
NOP
NOP
NOP
Tn
Tn+1
CKE
WL = RL - 1 = 2
WL + BL/2 + WR
NOP
NOP
Act.PD 3
WR
tIS
Tn+2
tIS
Valid
Command
Active
Power-Down
Exit
tXARD or
tXARDS *)
CK, CK
DIN A0 DIN A1 DIN A2 DIN A3
Active
Power-Down
Entry
相關(guān)PDF資料
PDF描述
HYB18T256160AF-37 256 Mbi t DDR2 SDRAM
HYB18T256160AF-5 256 Mbi t DDR2 SDRAM
HYB18T256160AL-3S 256 Mbi t DDR2 SDRAM
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