參數(shù)資料
型號: HYB25D128800ATL-6
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit Double Data Rate SDRAM
中文描述: 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 12/85頁
文件大?。?/td> 3085K
代理商: HYB25D128800ATL-6
input data during a Write access. DM is sampled on both
edges of DQS. Although DM pins are input only, the DM
loading matches the DQ and DQS loading.
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Pin Configuration
Data Sheet
12
Rev. 1.0, 2004-04
Data Signals
×
8 organization
A8, 2
B7, 5
C7, 8
D7, 11
D3, 56
C3, 59
B3, 62
A2, 65
Data Strobe
×8
organisation
E3, 51
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal Bus 7:0
DQS
I/O
SSTL
Data Strobe
Note:Output with read data, input with write data. Edge-aligned
with read data, centered in write data. Used to capture write
data.
Data Mask
×
8 organization
F3, 47
DM
I
SSTL
Data Mask
Note:DM is an input mask signal for write data. Input data is
masked when DM is sampled HIGH coincident with that
Data Signals
×
16 organization
A8, 2
B9, 4
B7, 5
C9, 7
C7, 8
D9, 10
D7, 11
E9, 13
E1, 54
D3, 56
D1, 57
C3, 59
C1, 60
B3, 62
B1, 63
A2, 65
Data Strobe
×
16 organization
E3, 51
E7, 16
Data Mask
×
16 organization
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
SSTL
Data Signal 15:0
UDQS
LDQS
I/O
I/O
SSTL
SSTL
Data Strobe Upper Byte
Data Strobe Lower Byte
Table 2
Ball#/Pin#
Pin Configuration of DDR SDRAM
Name
Pin
Type
Buffer
Type
Function
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