- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄370783 > HYB25D128800ATL-6 (INFINEON TECHNOLOGIES AG) 128 Mbit Double Data Rate SDRAM PDF資料下載
參數(shù)資料
| 型號： | HYB25D128800ATL-6 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 128 Mbit Double Data Rate SDRAM |
| 中文描述： | 128兆雙倍數(shù)據(jù)速率SDRAM |
| 文件頁數(shù)： | 21/85頁 |
| 文件大小： | 3085K |
| 代理商： | HYB25D128800ATL-6 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁
Data Sheet
21
Rev. 1.0, 2004-04
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
3.2
Mode Register Definition
The Mode Register is used to define the specific mode of operation of the DDR SDRAM. This definition includes
the selection of a burst length, a burst type, a CAS latency, and an operating mode. The Mode Register is
programmed via the Mode Register Set command (with BA0 = 0 and BA1 = 0) and retains the stored information
until it is programmed again or the device loses power (except for bit A8, which is self-clearing).
Mode Register bits A0-A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4-
A6 specify the CAS latency, and A7-A11 specify the operating mode.
The Mode Register must be loaded when all banks are idle, and the controller must wait the specified time before
initiating the subsequent operation. Violating either of these requirements results in unspecified operation.
3.2.1
Read and write accesses to the DDR SDRAM are burst oriented, with the burst length being programmable. The
burst length determines the maximum number of column locations that can be accessed for a given Read or Write
command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types.
Burst Length
MR
Mode Register Definition
(BA[1:0] = 00
B
)
BA1
BA0
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
0
0
MODE
CL
BT
BL
reg. addr
w
w
w
w
Field
BL
Bits
[2:0]
Type
1)
w
1) w = write
Description
Burst Length
Number of sequential bits per DQ related to one read/write command; see
Chapter 3.2.1
.
Note:All other bit combinations are RESERVED.
001 2
010 4
011 8
Burst Type
See
Table 5
for internal address sequence of low order address bits; see
Chapter 3.2.2
.
0
Sequential
1
Interleaved
CAS Latency
Number of full clocks from read command to first data valid window; see
Chapter 3.2.3
.
Note:All other bit combinations are RESERVED.
BT
3
w
CL
[6:4]
w
010 2
011 3
101 1.5
Note:DDR200 components only
110 2.5
Operating Mode
See
Chapter 3.2.4
.
Note:All other bit combinations are RESERVED.
MODE
[12:7] w
000000
000010
Normal Operation without DLL Reset
Normal Operation with DLL Reset
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYB25D128400ATL-7 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128800ATL-7 | 128 Mbit Double Data Rate SDRAM |
| HYB25D128160TCL-75 | MEMORY SPECTRUM |
| HYB25D128160TCL-7F | MEMORY SPECTRUM |
| HYB25D128160TE-37 | MEMORY SPECTRUM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYB25D128800ATL-7 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800ATL-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:128 Mbit Double Data Rate SDRAM |
| HYB25D128800C | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM |
| HYB25D128800CC-5 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM |
| HYB25D128800CC-6 | 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:128-Mbit Double-Data-Rate SDRAM |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。