參數(shù)資料
型號: HYB25D128800ATL-6
廠商: INFINEON TECHNOLOGIES AG
英文描述: 128 Mbit Double Data Rate SDRAM
中文描述: 128兆雙倍數(shù)據(jù)速率SDRAM
文件頁數(shù): 46/85頁
文件大小: 3085K
代理商: HYB25D128800ATL-6
HYB25D128[400/800/160]C[C/E/T](L)
128 Mbit Double Data Rate SDRAM
Functional Description
Data Sheet
46
Rev. 1.0, 2004-04
Figure 24
Write to Read: Min. DQSS, Odd Number of Data (3-bit Write), Interrupting (CL2; BL8)
DI a-b = data in for bank a, column b.
An interrupted burst is shown, 3 data elements are written.
2 subsequent elements of data in are applied in the programmed order following DI a-b.
t
WTR
is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)
The Read command masks the last 2 data elements in the burst.
A10 is Low with the Write command (Auto Precharge is disabled).
The Read and Write commands are not necessarily to the same bank.
1 = This bit is correctly written into the memory array if DM is low.
2 = These bits are incorrectly written into the memory array if DM is low.
Don’t Care
T1
T2
T3
T4
T5
T6
NOP
NOP
NOP
Read
Write
NOP
CK
CK
Command
Address
BAa, COL b
BAa, COL n
t
WTR
DI a-b
DQS
DQ
CL = 2
t
DQSS
(min)
DM
1
2
2
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