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參數(shù)資料
| 型號： | HYB39S16800CT-8 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 16 MBit Synchronous DRAM |
| 中文描述： | 2M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO50 |
| 封裝： | 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50 |
| 文件頁數(shù)： | 11/19頁 |
| 文件大?。?/td> | 101K |
| 代理商： | HYB39S16800CT-8 |
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
11
1998-10-01
DQM Function
DQM has two functions for data I/O read write operations. During reads, when it turns to high at a
clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency
t
DQZ
). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency
t
DQW
= zero clocks).
Suspend Mode
During normal access mode, CKE is held high and CLK is enabled. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency
t
CSL
).
Power Down
In order to reduce standby power consumption, a power down mode is available. Bringing CKE low
enters the power down mode and all of receiver circuits are gated. All banks must be precharged
before entering this mode. One clock delay is required for mode entry and exit. The Power Down
mode does not perform any refresh operation.
Auto Precharge
Two methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the
Read with Auto Precharge
function is initiated. The SDRAM automatically enters the precharge operation one clock before the
last data out for CAS latency 2 amd two clocks for CAS latency 3. If CAS10 is high when a Write
Command is issued, the
Write with Auto Precharge function
is initiated. The SDRAM
automatically enters the precharge operation one clock delay form the last data-in for CAS latencies
of 1 and 2 and two clocks for CAS latencies of 3. This delay is referenced as
t
DPL
.
Precharge Command
If CA10 is low, the chip needs another way to precharge. In this mode, a separate precharge
command is necessary. When RAS and WE are low and CAS is high at a clock timing, it triggers the
precharge operation. Two address bits, A10 and A11, are used to define banks as shown in the
following list. The precharge command may be applied coincident with the last of burst reads for
CAS Latency = 1 and with the second to the last read data for CAS Latencies = 2 & 3. Writes require
a time
t
WR
from the last burst data to apply the precharge command.
Bank Selection by Address Bits
A10
Low
Low
High
A11
Low
High
Don’t Care
Bank A only
Bank B only
Both A and B
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PDF描述 |
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