參數(shù)資料
型號(hào): HYB39S16800CT-8
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 16 MBit Synchronous DRAM
中文描述: 2M X 8 SYNCHRONOUS DRAM, 6 ns, PDSO50
封裝: 0.400 INCH, 0.80 MM PITCH, PLASTIC, TSOP-50
文件頁(yè)數(shù): 14/19頁(yè)
文件大?。?/td> 101K
代理商: HYB39S16800CT-8
HYB 39S16400/800/160CT-8/-10
16 MBit Synchronous DRAM
Semiconductor Group
14
1998-10-01
Notes
1. The specified values are valid when addresses are changed no more than three times during
t
RC(MIN.)
and when No Operation commands are registered on every rising clock edge during
t
RC(MIN)
.
2. The specified values are valid when data inputs (DQ’s) are stable during
t
RC(MIN.)
.
Operating Currents
T
A
= 0 to 70
o
C,
V
CC
= 3.3 V
±
0.3 V
(Recommended Operating Conditions unless otherwise noted)
Parameter
Symbol Test Condition
CAS
Latency
-8
-10
Unit Note
max.
max.
Operating current
I
CC1
Burst Length = 4
t
RC
t
RC(MIN.,
t
CK
t
CK(MIN.)
,
I
O
= 0 mA
2 bank interleave operation
CKE
V
IL(MAX.)
,
t
CK
t
CK(MIN.)
CKE
V
IL(MAX.)
,
t
CK
= infinite
2
3
100
115
80
90
mA
mA
1, 2
Precharge
Standby current in
power down mode
I
CC2P
I
CC2PS
2
2
mA
1
1
mA
Precharge standby
current in non-
power down mode
I
CC2N
CKE
V
IH(MIN.)
,
t
CK
t
CK(MIN.)
input signals changed once in
3 cycles
CKE
V
IH(MIN.)
,
t
CK
= infinite,
input signals are stable
CKE
V
IL(MAX).
,
t
CK
t
CK(MIN.)
CKE
V
IL(MAX.)
,
t
CK
= infinite,
input signals are stable
CKE
V
IH(MIN.)
,
t
CK
t
CK(MIN.)
,
changed once in 3 cycles
CKE
V
IH(MIN.)
,
t
CK
= infinite,
input signals are stable
15
15
mA
CS=
High
I
CC2NS
5
5
mA
Active standby
current in power
down mode
I
CC3P
I
CC3PS
3
3
mA
2
2
mA
Active standby
current in non-
power down mode
I
CC3N
25
25
mA
CS=
High,
1
I
CC3NS
15
15
mA
Burst operating
current
I
CC4
Burst Length = full page
t
RC
= infinite
t
CK
t
CK(MIN.)
,
I
O
= 0 mA
2 banks activated
t
RC
t
RC(MIN.)
2
3
60
70
50
60
mA
1, 2
Auto (CBR) refresh
current
I
CC5
2
3
60
70
50
60
mA
mA
1, 2
Self refresh
I
CC6
CKE
0.2 V
1
1
mA
1, 2
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