參數(shù)資料
型號(hào)： IBM25405GP-3BA200C2
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA456
封裝： PLASTIC, BGA-456
文件頁(yè)數(shù)： 21/48頁(yè)
文件大?。?/td> 649K
代理商： IBM25405GP-3BA200C2
PowerPC 405GP Embedded Controller
Data Sheet
Advance Information
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 28 of 48
galdsh5f
06/15/99 Preliminary
AC24
AB24
BA1
BA0
Bank Address supporting up to 4 internal
banks
O
3.3V LVTTL
35
A
AF24
RAS
Row Address Strobe
O
3.3V LVTTL
35
A
AB23
CAS
Column Address Strobe
O
3.3V LVTTL
35
A
AC12
AC10
AC6
AA3
DQM0
DQM1
DQM2
DQM3
DQM for byte lanes 0, 1, 2, and 3
O
3.3V LVTTL
35
C
AC15
DQMCB
DQM for ECC check bits
O
3.3V LVTTL
35
C
AE14
AF15
AF14
AD13
AF13
AF12
AE13
AD12
ECC0
ECC1
ECC2
ECC3
ECC4
ECC5
ECC6
ECC7
ECC check bits 0:7
I/O
3.3V LVTTL
35
C
4
AD17
AF17
AE15
AC14
BankSel0
BankSel1
BankSel2
BankSel3
Select up to four external SDRAM banks
O
3.3V LVTTL
35
C
AC16
WE
Write Enable
O
3.3V LVTTL
35
A
AB25
AC25
ClkEn0
ClkEn1
SDRAM Clock Enable
O
3.3V LVTTL
20
C
AC26
AA23
MemClkOut0
MemClkOut1
Two copies of an SDRAM clock allows, in
some cases, glueless SDRAM attach without
requiring this signal to be repowered by a PLL
or zero-delay buffer.
O
3.3V LVTTL
35
B
AF4
MemClkIn
Reserved - Future versions of 405GP may use
this input SDRAM clock to “self-clock”
incoming SDRAM data
I
3.3V LVTTL
Rcvr
n/a
A
4
Pin Functional Description 35mm, 456-Ball Enhanced Plastic Ball Grid Array Package (Part 5 of 14)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k to 5V)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input, pull-up or pull-down required
Ball
Signal Name
Description
I/O
Type
Imped
ance
(
)
BHC
Notes
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