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參數(shù)資料
| 型號(hào)： | IBM25405GP-3BA200C2 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數(shù)： | 24/48頁 |
| 文件大小： | 649K |
| 代理商： | IBM25405GP-3BA200C2 |
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PowerPC 405GP Embedded Controller
Data Sheet
Advance Information
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 30 of 48
galdsh5f
06/15/99 Preliminary
D5
A3
B4
B5
D6
B6
C6
D7
A5
B7
C7
D8
B8
C8
D9
A8
C9
D10
C10
A10
D11
B12
D13
D12
B13
A12
A13
C14
A14
A15
C15
D15
PerAddr0
PerAddr1
PerAddr2
PerAddr3
PerAddr4
PerAddr5
PerAddr6
PerAddr7
PerAddr8
PerAddr9
PerAddr10
PerAddr11
PerAddr12
PerAddr13
PerAddr14
PerAddr15
PerAddr16
PerAddr17
PerAddr18
PerAddr19
PerAddr20
PerAddr21
PerAddr22
PerAddr23
PerAddr24
PerAddr25
PerAddr26
PerAddr27
PerAddr28
PerAddr29
PerAddr30
PerAddr31
Peripheral address bus used by 405GP when
not in external master mode, otherwise used
by external master.
I/O
5V tolerant
3.3V LVTTL
35
B
1
D3
G4
G3
E1
PerPar0
PerPar1
PerPar2
PerPar3
Peripheral byte parity signals
I/O
5V tolerant
3.3V LVTTL
35
B
1
D2
E2
F4
D1
PerWBE0
PerWBE1
PerWBE2
PerWBE3
As outputs, these pins can act as byte-enables
which are valid for an entire cycle or as write-
byte-enables which are valid for each byte on
each data transfer, allowing partial word
transactions. As outputs, pins are used by
either peripheral controller or DMA controller
depending upon the type of transfer involved.
Used as inputs when external bus master
owns the external interface
I/Ot
5V tolerant
3.3V LVTTL
50
B
1, 2
B3
PerCS0
Peripheral chip select bank 0
O
5V tolerant
3.3V LVTTL
50
B
2
C4
C5
A4
B9
B10
A9
B11
PerCS1[GPIO10]
PerCS2[GPIO11]
PerCS3[GPIO12]
PerCS4[GPIO13]
PerCS5[GPIO14]
PerCS6[GPIO15]
PerCS7[GPIO16]
Seven additional peripheral chip selects
or
General Purpose I/O - To access this function,
software must toggle a DCR register bit.
O[I/O]
5V tolerant
3.3V LVTTL
[mux’d]
50
B
1,2
Pin Functional Description 35mm, 456-Ball Enhanced Plastic Ball Grid Array Package (Part 7 of 14)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k to 5V)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input, pull-up or pull-down required
Ball
Signal Name
Description
I/O
Type
Imped
ance
(
)
BHC
Notes
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