參數(shù)資料
型號： IBM25405GP-3BA200C2
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA456
封裝： PLASTIC, BGA-456
文件頁數(shù)： 25/48頁
文件大?。?/td> 649K
代理商： IBM25405GP-3BA200C2
PowerPC 405GP Embedded Controller
Advance Information
Data Sheet
galdsh5f
06/15/99 Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 31 of 48
C2
PerOE
Used by either peripheral controller or DMA
controller depending upon the type of transfer
involved. When the 405GP is the bus master it
enables the selected SDRAMs to drive the
bus.
O
5V tolerant
3.3V LVTTL
50
B
2
C1
PerR/W
Used by 405GP when not in external master
mode as output by either the peripheral
controller or DMA controller depending upon
the type of transfer involved. High indicates a
read from memory, low indicates a write to
memory.
Otherwise it used by the external master as an
input to indicate the direction of transfer.
I/O
5V tolerant
50
B
1, 2
E3
PerReady
Used by a peripheral slave to indicate it is
ready to transfer data
I
5V tolerant
Rcvr
n/a
A
1, 2
F2
PerBLast
Used by 405GP when not in external master
mode, otherwise used by external master.
Indicates the last transfer of a memory access.
I/O
5V tolerant
3.3V LVTTL
50
B
1, 4
C16
D14
C11
A7
DMAReq0
DMAReq1
DMAReq2
DMAReq3
DMAReq0:3 are used by slave peripherals to
indicate they are prepared to transfer data.
I
5V tolerant
Rcvr
n/a
A
1, 5
D16
B15
B14
C12
DMAAck0
DMAAck1
DMAAck2
DMAAck3
DMAAck0:3 are used by 405GP to indicate
that data transfers have occurred.
O
5V tolerant
3.3V LVTTL
50
B
6
F3
G2
V2
Y1
EOT0[TC0]
EOT1[TC1]
EOT2[TC2]
EOT3[TC3]
End Of Transfer/Terminal Count
I/O
5V tolerant
3.3V LVTTL
50
B
1, 5
External MASTER Peripheral Interface (Number of pins = 9)
E4
PerClk
Peripheral clock to be used by an external
master and by synchronous peripheral slaves
O
5V tolerant
3.3V LVTTL
35
B
T3
ExtReset
Peripheral reset to be used by an external
master and by synchronous peripheral slaves
O
5V tolerant
3.3V LVTTL
35
B
V1
HoldReq
Hold Request, used by an external master to
request ownership of the peripheral bus
I
5V tolerant
Rcvr
n/a
A
1, 5
U2
HoldAck
Hold Acknowledge, used by 405GP to transfer
ownership of peripheral bus to an external
master
O
5V tolerant
3.3V LVTTL
50
B
6
Y4
ExtReq
ExtReq is used by an external master to
indicate it is prepared to transfer data
I
5V tolerant
Rcvr
n/a
A
1, 4
Y3
ExtAck
ExtAck is used by 405GP to indicate that a
data transfer occurred.
O
5V tolerant
3.3V LVTTL
50
B
6
Pin Functional Description 35mm, 456-Ball Enhanced Plastic Ball Grid Array Package (Part 8 of 14)
Multiplexed signals are shown in brackets following the first signal name assigned to each multiplexed ball.
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3k
to 3.3V, 10k to 5V)
3. Must pull down (recommended value is 1k
)
4. If not used, must pull up (recommended value is 3k
to 3.3V)
5. If not used, must pull down (recommended value is 1k
)
6. Strapping input, pull-up or pull-down required
Ball
Signal Name
Description
I/O
Type
Imped
ance
(
)
BHC
Notes
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