參數(shù)資料
型號(hào)： IBM25405GP-3BA200C2
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA456
封裝： PLASTIC, BGA-456
文件頁(yè)數(shù)： 46/48頁(yè)
文件大小： 649K
代理商： IBM25405GP-3BA200C2
PowerPC 405GP Embedded Controller
Advance Information
Data Sheet
galdsh5f
06/15/99 Preliminary
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 48
PLB to PCI Interface
The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC
processor and local memory. This interface is compliant with version 2.2 of the PCI Specification.
Features of this core include:
Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use
is optional and may be disabled for systems which employ an external arbiter.
PLB 3.0 Compliant
PLB bus frequency up to 100MHz
64-bit PLB Master
32-bit PLB Slave
PCI bus frequency up to 66MHz
Synchronous operation at 1/n fractions of PLB speed (n = 1 to 4) to 33MHz maximum
Asynchronous operation from 1/8 PLB frequency to 66MHz maximum
32-bit PCI Address/Data Bus
Power Management:
PCI Bus Power Management v1.1 compliant
Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI
Buffering between PLB and PCI:
PCI Target 64-byte write post buffer
PCI Target 96-byte read prefetch buffer
PLB Slave 8-byte write post buffer
PLB Slave 64-byte read prefetch buffer
Error tracking/status
Supports PCI Target side conguration
Supports processor access to all PCI address spaces:
Single-byte PCI I/O reads and writes
PCI memory single-beat and prefetch-burst reads and single-beat writes
Single-byte PCI conguration reads and writes (type 0 and type 1)
PCI interrupt acknowledge
PCI special cycle
Supports PCI target access to all PLB address spaces
Supports PowerPC processor boot from PCI memory
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