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參數(shù)資料
| 型號(hào)： | IBM25405GP-3BA200C2 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC PROCESSOR, PBGA456 |
| 封裝： | PLASTIC, BGA-456 |
| 文件頁數(shù)： | 47/48頁 |
| 文件大?。?/td> | 649K |
| 代理商： | IBM25405GP-3BA200C2 |
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PowerPC 405GP Embedded Controller
Data Sheet
Advance Information
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 8 of 48
galdsh5f
06/15/99 Preliminary
SDRAM Memory Controller
The PPC405GP Memory Controller core provides a low latency access path to SDRAM memory. A variety of
system memory configurations are supported. The memory controller supports up to four logical banks. Up to
256 MB per bank are supported, up to a maximum of 1 GB. Memory timings, address and bank sizes, and
memory addressing modes are programmable.
Synchronous DRAM:
11x8 to 13x11 addressing for SDRAM (2- and 4-bank)
Memory bus operates at same frequency as PLB
32-bit memory interface support
Programmable address compare for each bank of memory
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4 GB address space
Industry standard 168-pin DIMMS are supported (some congurations)
Up to 100MHz Memory, includes PC100 support
4 MB to 256 MB per bank
Programmable address mapping and timing
Auto refresh
Page Mode Accesses with up to 4 open pages
Sync DRAM conguration via mode set command
Power Management (self-refresh)
ECC support
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Standard SEC/DED coverage
-
Aligned nibble error detect
-
Address error logging
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Mixed ECC/non-ECC banks
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Bypass mode
External Peripheral Bus Controller (EBC)
Up to eight ROM, EPROM, SRAM, Flash, and Slave Peripheral I/O banks supported
Up to 50 MHz operation
Burst and non-burst devices
8-, 16-, 32-bit byte-addressable data bus width support
Latch data on Ready, Synchronous or Asynchronous
Programmable 2K clock time-out counter with disable for Ready
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