參數(shù)資料
型號(hào)： IDT72V261LA
廠商： Integrated Device Technology, Inc.
英文描述： 3.3 VOLT CMOS SuperSync FIFO
中文描述： 3.3伏的CMOS SuperSync先進(jìn)先出
文件頁(yè)數(shù)： 13/27頁(yè)
文件大?。?/td> 310K
代理商： IDT72V261LA
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WRITE CLOCK (WCLK)
A write cycle is initiated on the rising edge of the WCLK input. Data
setup and hold times must be met with respect to the LOW-to-HIGH
transition of the WCLK. It is permssible to stop the WCLK. Note that
while WCLK is idle, the
FF
/
IR
,
PAF
and
HF
flags will not be updated.
(Note that WCLK is only capable of updating
HF
flag to LOW.) The
Write and Read Clocks can either be independent or coincident.
WRITE ENABLE (
WEN
)
When the
WEN
input is LOW, data may be loaded into the FIFO
RAMarray on the rising edge of every WCLK cycle if the device is not
full. Data is stored in the RAMarray sequentially and independently of
any ongoing read operation.
When
WEN
is HIGH, no new data is written in the RAMarray on
each WCLK cycle.
To prevent data overflow in the IDT Standard mode,
FF
will go LOW,
inhibiting further write operations. Upon the completion of a valid read
cycle,
FF
will go HIGH allowing a write to occur. The
FF
is updated by
two WCLK cycles + t
SKEW
after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR
will go HIGH,
inhibiting further write operations. Upon the completion of a valid read
cycle,
IR
will go LOW allowing a write to occur. The
IR
flag is updated
by two WCLK cycles + t
SKEW
after the valid RCLK cycle.
WEN
is ignored when the FIFO is full in either FWFT or IDT Standard
mode.
READ CLOCK (RCLK)
A read cycle is initiated on the rising edge of the RCLK input. Data
can be read on the outputs, on the rising edge of the RCLK input. It is
permssible to stop the RCLK. Note that while RCLK is idle, the
EF
/
OR
,
PAE
and
HF
flags will not be updated. (Note that RCLK is only capable
of updating the
HF
flag to HIGH.) The Write and Read Clocks can be
independent or coincident.
READ ENABLE (
REN
)
When Read Enable is LOW, data is loaded fromthe RAMarray into
the output register on the rising edge of every RCLK cycle if the device
is not empty.
When the
REN
input is HIGH, the output register holds the previous
data and no new data is loaded into the output register. The data
outputs Q
0
-Q
n
maintain the previous data value.
In the IDT Standard mode, every word accessed at Q
n
, including the
first word written to an empty FIFO, must be requested using
REN
.
When the last word has been read fromthe FIFO, the Empty Flag (
EF
)
will go LOW, inhibiting further read operations.
REN
is ignored when
the FIFO is empty. Once a write is performed,
EF
will go HIGH allowing
a read to occur. The
EF
flag is updated by two RCLK cycles + t
SKEW
after the valid WCLK cycle.
In the FWFT mode, the first word written to an empty FIFO automati-
cally goes to the outputs Q
n
, on the third valid LOW to HIGH transition
of RCLK + t
SKEW
after the first write.
REN
does not need to be
asserted LOW. In order to access all other words, a read must be
executed using
REN
. The RCLK LOW to HIGH transition after the last
word has been read fromthe FIFO, Output Ready (
OR
) will go HIGH
with a true read (RCLK with
REN
= LOW), inhibiting further read opera-
tions.
REN
is ignored when the FIFO is empty.
SERIAL ENABLE (
SEN
)
The
SEN
input is an enable used only for serial programmng of the
offset registers. The serial programmng method must be selected
during Master Reset.
SEN
is always used in conjunction with
LD
.
When these lines are both LOW, data at the SI input can be loaded into
the programregister one bit for each LOW-to-HIGH transition of WCLK.
(See Figure 4.)
When
SEN
is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN
functions the same way in
both IDT Standard and FWFT modes.
OUTPUT ENABLE (
OE
)
When Output Enable is enabled (LOW), the parallel output buffers
receive data fromthe output register. When
OE
is HIGH, the output
data bus (Q
n
) goes into a high impedance state.
LOAD (
LD
)
This is a dual purpose pin. During Master Reset, the state of the
LD
input determnes one of two default offset values (127 or 1,023) for the
PAE
and
PAF
flags, along with the method by which these offset regis-
ters can be programmed, parallel or serial. After Master Reset,
LD
enables write operations to and read operations fromthe offset regis-
ters. Only the offset loading method currently selected can be used to
write to the registers. Offset registers can be read only in parallel. A
LOW on
LD
during Master Reset selects a default
PAE
offset value of
07FH (a threshold 127 words fromthe empty boundary), a default
PAF
offset value of 07FH (a threshold 127 words fromthe full boundary),
and parallel loading of other offset values. A HIGH on
LD
during
Master Reset selects a default
PAE
offset value of 3FFH (a threshold
1,023 words fromthe empty boundary), a default
PAF
offset value of
3FFH (a threshold 1,023 words fromthe full boundary), and serial load-
ing of other offset values.
After Master Reset, the
LD
pin is used to activate the programmng
process of the flag offset values
PAE
and
PAF
. Pulling
LD
LOW will
begin a serial loading or parallel load or read of these offset values.
See Figure 4,
Programmable Flag Offset Programmng Sequence
.
OUTPUTS:
FULL FLAG (
FF
/
IR
)
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF
)
function is selected. When the FIFO is full,
FF
will go LOW, inhibiting
further write operations. When
FF
is HIGH, the FIFO is not full. If no
reads are performed after a reset (either
MRS
or
PRS
),
FF
will go LOW
after D writes to the FIFO (D = 16,384 for the IDT72V261LA and 32,768
for the IDT72V271LA). See Figure 7,
Write Cycle and Full Flag Timng
(IDT Standard Mode)
, for the relevant timng information.
In FWFT mode, the Input Ready (
IR
) function is selected.
IR
goes
LOW when memory space is available for writing in data. When there
is no longer any free space left,
IR
goes HIGH, inhibiting further write
operations. If no reads are performed after a reset (either
MRS
or
PRS
),
IR
will go HIGH after D writes to the FIFO (D = 16,385 for the
IDT72V261LA and 32,769 for the IDT72V271LA) See Figure 9,
Write
Timng (FWFT Mode)
, for the relevant timng information.
The
IR
status not only measures the contents of the FIFO memory,
but also counts the presence of a word in the output register. Thus, in
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參數(shù)描述
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IDT72V261LA10TF 功能描述:IC FIFO SS 8192X18 10NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
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