參數(shù)資料
型號(hào)： IDT72V261LA
廠商： Integrated Device Technology, Inc.
英文描述： 3.3 VOLT CMOS SuperSync FIFO
中文描述： 3.3伏的CMOS SuperSync先進(jìn)先出
文件頁(yè)數(shù)： 3/27頁(yè)
文件大?。?/td> 310K
代理商： IDT72V261LA
IDT72V261LA/72V271LA
3.3 VOLT CMOS SuperSync FIFO 16,384 x 9 and 32,768 x 9
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
DESCRIPTION (CONTINUED)
There are two possible timng modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In
IDT Standard mode,
the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating
REN
and
enabling a rising RCLK edge, will shift the word frominternal memory to
the data output lines.
In
FWFT mode,
the first word written to an empty FIFO is clocked
directly to the data output lines after three transitions of the RCLK signal. A
REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on
REN
for
access. The state of the FWFT/SI input during Master Reset determnes
the timng mode in use.
For applications requiring more data storage capacity than a single
FIFO can provide, the FWFT timng mode permts depth expansion by
chaining FIFOs in series (i.e. the data outputs of one FIFO are connected
to the corresponding data inputs of the next). No external logic is re-
quired.
These FIFOs have five flag pins,
EF
/
OR
(Empty Flag or Output Ready),
FF
/
IR
(Full Flag or Input Ready),
HF
(Half-full Flag),
PAE
(Programmable
Almost-Empty flag) and
PAF
(Programmable Almost-Full flag). The
EF
and
FF
functions are selected in IDT Standard mode. The
IR
and
OR
functions are selected in FWFT mode.
HF
,
PAE
and
PAF
are always
available for use, irrespective of timng mode.
PAE
and
PAF
can be programmed independently to switch at any point
in memory. (See Table 1 and Table 2.) Programmable offsets determne
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that
PAE
can be
set to switch at 127 or 1,023 locations fromthe empty boundary and the
PAF
threshold can be set at 127 or 1,023 locations fromthe full boundary.
These choices are made with the
LD
pin during Master Reset.
Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO
DATA OUT (Q
0
- Q
n
)
DATA IN (D
0
- D
n
)
MASTER RESET (
MRS
)
READ CLOCK (RCLK)
READ ENABLE (
REN
)
OUTPUT ENABLE (
OE
)
EMPTY FLAG/OUTPUT READY (
EF
/
OR
)
PROGRAMMABLE ALMOST-EMPTY (
PAE
)
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN
)
LOAD (
LD
)
FULL FLAG/INPUT READY (
FF
/
IR
)
PROGRAMMABLE ALMOST-FULL (
PAF
)
IDT
72V261LA
72V271LA
PARTIAL RESET (
PRS
)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (
RT
)
4673 drw 03
HALF FULL FLAG (
HF
)
SERIAL ENABLE(
SEN
)
For serial programmng,
SEN
together with
LD
on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programmng,
WEN
together with
LD
on each rising edge of WCLK,
are used to load the offset registers via Dn.
REN
together with
LD
on each
rising edge of RCLK can be used to read the offsets in parallel fromQn
regardless of whether serial or parallel offset loading has been selected.
During Master Reset (
MRS
) the following events occur: The read and
write pointers are set to the first location of the FIFO. The FWFT pin
selects IDT Standard mode or FWFT mode. The
LD
pin selects either a
partial flag default setting of 127 with parallel programmng or a partial flag
default setting of 1,023 with serial programmng. The flags are updated
according to the timng mode and default offsets selected.
The Partial Reset (
PRS
) also sets the read and write pointers to the first
location of the memory. However, the timng mode, partial flag program-
mng method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timng mode and offsets in effect.
PRS
is useful for resetting a device in
md-operation, when reprogrammng partial flags would be undesirable.
The Retransmt function allows data to be reread fromthe FIFO more
than once. A LOW on the
RT
input during a rising RCLK edge initiates a
retransmt operation by setting the read pointer to the first location of the
memory array.
If, at any time, the FIFO is not actively performng an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is mnimzed. Initiating any operation (by acti-
vating control inputs) will immediately take the device out of the power
down state.
The IDT72V261LA/72V271LA are fabricated using IDT’s high speed
submcron CMOS technology.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72V261LA10PF 功能描述:IC FIFO SS 8192X18 10NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF
IDT72V261LA10PF8 功能描述:IC FIFO SS 8192X18 10NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF
IDT72V261LA10PFG 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 10NS 64TQFP 制造商:Integrated Device Technology Inc 功能描述:IC FIFO 144K 16KX9 3.3V TQFP64 制造商:Integrated Device Technology Inc 功能描述:IC, FIFO, 144K, 16KX9, 3.3V, TQFP64
IDT72V261LA10PFG8 制造商:Integrated Device Technology Inc 功能描述:IC FIFO SS 8192X18 10NS 64TQFP
IDT72V261LA10TF 功能描述:IC FIFO SS 8192X18 10NS 64QFP RoHS:否 類(lèi)別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲(chǔ)容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問(wèn)時(shí)間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤(pán) 其它名稱(chēng):72271LA10PF
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