- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67713 > IDT74CV105BPV (INTEGRATED DEVICE TECHNOLOGY INC) 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT74CV105BPV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁(yè)數(shù)： | 18/21頁(yè) |
| 文件大?。?/td> | 94K |
| 代理商： | IDT74CV105BPV |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)當(dāng)前第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)
COMMERCIALTEMPERATURERANGE
6
IDTCV105B
CLOCKGENERATORFORDESKTOPPCPLATFORMS
ONECYCLE INDEX BLOCK READ
Bit
# of bits
From
Description
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Acknowledge
11-18
8
Master
Registeroffsetbyte(startingbyte)
19
1
Slave
Acknowledge
20-27
8
Master
1xxxxxxx. Bit[20] = 1, followed with byte
count, which will be stored into I2C table byte 8.
28
1
Slave
Acknowledge
29
1
Master
Repeatedstart
30-37
8
Master
D3h
38
1
Slave
Acknowledge
39-46
8
Slave
Byte count, N, I2C table byte 8 value. Power
on default is 0FH[15].
47
1
Master
Acknowledge
48-55
8
Slave
Offsetdatabyte,specifiedbybit[11:18]
56
1
Master
Acknowledge
57-64
8
Slave
Offset + 1 data byte
:
Slave
Offset + N-2
Master
Acknowledge
Slave
Offset + N-1
Notacknowledge
Stop
BYTE READ METHODS (CHOSE ONE):
Use IDT OneCycle Index Block Read, bit[20:27] = 10000001.
Notice that byte count register (byte 8) will be changed to 0IH.
Use Index Block Write protocol to change byte count (byte 8) to
1. After that, use Index Block Read.
TO CHANGE BYTE 8 VALUE:
Use IDT OneCycle Index Block Read, as above
Use Index Block Write protocol to change byte 8 value.
SM BUS PROTOCOL
INDEX BLOCK READ PROTOCOL
Bit
# of bits
From
Description
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Acknowledge
11-18
8
Master
Registeroffsetbyte(startingbyte)
19
1
Slave
Acknowledge
20
1
Master
Repeatedstart
21-28
8
Master
D3h
29
1
Slave
Acknowledge
30-37
8
Slave
Byte count, N, I2C table byte 8 value. Power
on default is 0FH[15].
38
1
Master
Acknowledge
39-46
8
Slave
Offsetdatabyte,specifiedbybit11-18
47
1
Master
Acknowledge
48-55
8
Slave
Offset + 1 data byte
:
Slave
Offset + N-2
Master
Acknowledge
Slave
Offset + N-1
Notacknowledge
Stop
INDEX BLOCK WRITE PROTOCOL
Bit
# of bits
From
Description
1
Master
Start
2-9
8
Master
D2h
10
1
Slave
Acknowledge
11-18
8
Master
Registeroffsetbyte(startingbyte)
19
1
Slave
Acknowledge
20-27
8
Master
Byte count N (0 is not a valid byte count)(1)
28
1
Slave
Acknowledge
29-36
8
Master
Firstdatabyte
37
1
Slave
Acknowledge
38-45
8
Master
Seconddatabyte
46
1
Slave
Acknowledge
:
Nth data byte
Stop
NOTE:
1. Bit [21:27] = byte count.
Bit 20 = 1, bit [21:27] will be stored into I2C table, Byte 8. SM Bus Byte 8 is read byte
count register, power on default is 0FH.
Bit 20 = 0, normal SM bus operation.
BYTE WRITE METHODS:
Setting bit[11:18] = starting address, bit [20:27] = 01H.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T100PY-T | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| IDT74FCT388915T100PYBG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| IDT74FCT388915T100LG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
| IDT74FCT388915T150LG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
| IDT74FCT388915T150LBG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FBT2240P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FBT2244P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FC138SO | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT131AP | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT138AD | 制造商:Integrated Device Technology Inc 功能描述: |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。