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參數(shù)資料
| 型號(hào)： | IDT74CV105BPV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 5/21頁 |
| 文件大?。?/td> | 94K |
| 代理商： | IDT74CV105BPV |
COMMERCIALTEMPERATURERANGE
IDTCV105B
CLOCKGENERATORFORDESKTOPPCPLATFORMS
13
BYTE 32: WD SOFT RESET TIMER
WD Soft Alarm timer has to be shorter than WD Hard Alarm timer. WDE and WD Soft Alarm bits, Byte 33 bit 7 and bit 5, have to be enabled for this Soft Alarm
function.
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
CPU WD Hard Alarm
0 = frequency select controlled by Byte 25 bit 7
HW/I2C
WDBS
RW
0
safefrequencymodeselect
1 = CPU frequency specified
WDCFS
by WDBS[2:0] WDCFS[2:0]
6
WDCFS2
CPU WD time out safe frequency select(1)
RW
0
5
WDCFS1
RW
0
4
WDCFS0
RW
0
3
WD soft alarm timer 3
Specify WD Soft Alarm Time Out time
RW
0
2
WD soft alarm timer 2
Time Out time = WD Soft Alarm Timer[3:0]*290ms
RW
0
1
WD soft alarm timer 1
Defaultis580ms.
RW
1
0
WD soft alarm timer 0
RW
0
NOTE:
1. See SW FREQUENCY SELECTION table.
BYTE 33: WD CONTROL
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
WDE
Watchdogenable
Disable
Enable
RW
0
6
WD FS relatch
Relatch HW FS2, 1, 0
Disable
Enable
RW
0
in event of WD Hard Alarm time out
5
WDSoftAlarmenable
Disable
Enable
RW
0
4
AGP/PCI WD Hard Alarm
In event of WD Hard Alarm time out
HW/I2C
WDAFS
RW
0
timeoutsafefrequencymodeselect 0 = AGP/PCI frequency controlled by Byte 30 bit 6
1 = AGP/PCI frequency specified by WDAFS[2:0]
3
SRC SMC 2
SRC SSC magnitude control(1)
1
2
SRC SMC 1
SRC SSC magnitude control(1)
0
1
SRC SMC 0
SRC SSC magnitude control(1)
1
0
Reserve
0
BYTE 34
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
SW 24_48MHz control override
0 = controlled by hardware, 1 = controlled by bit 6 HWcontrol controlledby
RW
0
bit 6
6
24_48MHzselect
48MHz
24MHz
RW
0
5
Reset#/PD#
Reset#/PD#modeselect
Reset#
PD#
RW
0
4
0
3
0
2
1
0
NOTE:
1. See SMC table.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT388915T100PY-T | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| IDT74FCT388915T100PYBG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
| IDT74FCT388915T100LG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
| IDT74FCT388915T150LG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
| IDT74FCT388915T150LBG | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), CQCC28 |
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