參數(shù)資料
型號(hào)： IDT74CV105BPV
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘產(chǎn)生/分配
英文描述： 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝： SSOP-48
文件頁(yè)數(shù)： 6/21頁(yè)
文件大?。?/td> 94K
代理商： IDT74CV105BPV
COMMERCIALTEMPERATURERANGE
14
IDTCV105B
CLOCKGENERATORFORDESKTOPPCPLATFORMS
CPU AND AGP CLOCK FREQUENCY SELECTION
Band switch will take effect only when WD Soft Alarm time out is issued, which means there is a RESET issued. Even if the user changed BS[2:0], if there
is no WD Soft Alarm, CPU PLL still uses the old band.
CPN[9:0] and APN[9:0] will be loaded into PLL only when CPN0 and APN0 are written respectively.
Byte 32 bit 7,
CPU WD Hard Alarm Time Out Frequency Select:
Byte 25 bit 7
00
Latched HW FS[1:0]
01
BS[2:0], CFS[2:0], Byte 25
10
WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32
11
WDBS[2:0], WDCFS[2:0], Byte 26 and Byte 32
WD SOFT AND HARD ALARM/TIME OUT OPERATION
WD HARD ALARM TIMER [7:0]
WD SOFT ALARM TIMER [3:0]
WDE
Trigger Watch Dog Circuit
WD SOFT ALARM TIME OUT
If WD Soft Alarm Enabled:
Set WDSRB
Issue RESET#
Switch CPU PLL band
WD HARD ALARM TIME OUT
Set WDHRB
Issue RESET#
Change CPU Frequency (see Byte 32, bit 7)
Change AGP/PCI Frequency (see Byte 33, bit 4)
If WD FS Relatch enabled, relatch HW FS2, FS1, FS0
Reset Byte 30 bit 7, and Byte 25 bit 0, to 0
User only uses WD Soft Alarm when there is a band switch. It can be from HW to SW select, or in the SW select with band change. Soft Alarm Timer has
to be shorter than Hard Alarm Timer.
AttheeventofWDHardAlarmtimeout,CPUSafereturnfrequencyisdecidedbytwobits:Byte32bit7andByte25bit7. AGP/PCISafeReturnFrequency
is decided by Byte 33 bit 4 and Byte 30 bit 6. Byte 30 bit 7, and Byte 25 bit 0, will be reset to 0.
Byte 33 bit 4,
AGP/PCI Hard Alarm Time Out Frequency Select:
Byte 30 bit 6
00
66/33MHz
01
AFS[2:0], Byte 28
10
WDAFS, Byte 28
11
WDAFS, Byte 28
CPU FREQUENCY
Byte 25 bit 0, bit 7
CPU Frequency Selected by:
00
HW FS[1:0]
01
BS[2:0], CFS[2:0], Byte 25
10
CPN[9:0] * Band Resolution
11
CPN[9:0] * Band Resolution
AGP/PCI FREQUENCY
Byte 30 bit 7, bit 6
AGP/PCI Frequency Selected by:
00
66/33
01
AFS[2:0], Byte 28
10
APN[9:0] * 0.223721591
11
APN[9:0] * 0.223721591
相關(guān)PDF資料
PDF描述
IDT74FCT388915T100PY-T FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28
IDT74FCT388915T100PYBG FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28
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