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參數(shù)資料
| 型號(hào)： | IDT74CV105BPV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 200 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁數(shù)： | 2/21頁 |
| 文件大?。?/td> | 94K |
| 代理商： | IDT74CV105BPV |
COMMERCIALTEMPERATURERANGE
10
IDTCV105B
CLOCKGENERATORFORDESKTOPPCPLATFORMS
BYTE 23
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
48MHz0
Outputenable
Tristate
Enable
RW
1
6
Outputenable
Tristate
Enable
RW
1
5
REF1
Outputenable
Tristate
Enable
RW
1
4
REF0
Outputenable
Tristate
Enable
RW
1
3
Reserve
1
2
48MHz1
Outputenable
Tristate
Enable
RW
1
Outputenable
Tristate
Enable
RW
1
0
Reserve
0
BYTE 24
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
WDHRB
WDhardalarmstatusreadback
R
6
WDSRB
WD softalarmstatusreadback
R
5
4
3
2
0
1
FSR1
HW FS1 read back
R
HW FS1
0
FSR0
HW FS0 read back
R
HW FS0
BYTE 25: CPU PLL CONTROL
Bit
Output(s)Affected
Description/Function
0
1
Type
Power On
7
CPU frequency band source select
0 = selected by HW latched FS[1:0], CFS[2:0]
HW
SW
RW
0
1 = selected by BS[2:0], CFS[2:0]
6
BS2, Band select 2
BS[2:0] CFS[2:0] select CPU frequency(1)
RW
0
5
BS1, Band select 1
BS[2:0] CFS[2:0] select CPU frequency(1)
RW
0
4
BS0, Band select 0
BS[2:0] CFS[2:0] select CPU frequency(1)
RW
0
3
CFS2
BS[2:0] CFS[2:0] select CPU frequency(1)
RW
0
2
CFS1
BS[2:0] CFS[2:0] select CPU frequency(1)
RW
0
1
CFS0
BS[2:0] CFS[2:0] select CPU frequency(1)
RW
0
CPU N Programming Enable
Disable
Enable
RW
0
NOTES:
1. See SW FREQUENCY SELECTION table.
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| IDT74FCT388915T100PY-T | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PDSO28 |
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