- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄377484 > IDT77301 (INTEGRATED DEVICE TECHNOLOGY INC) UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT77301 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 8 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 20/29頁 |
| 文件大小： | 342K |
| 代理商： | IDT77301 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁當(dāng)前第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁
IDT77301
UtopiaFIFO
1 to 4 (128 x 9 x 4) Demultiplexer-FIFO Commercial and Industrial Temperature Ranges
20
the CLAVR is asserted. On the next clock cycle, SOCR goes HIGH to
indicate the start of the next cell. Changing FIFO destinations result in only
a one clock cycle delay.
MULTICAST OPERATION
Configuration:
RMS =
“
1
”
indicates in-band routing.
MAS =
“
1
”
indicates multicast mode.
BSS =
“
0
”
18 bit operation
Operation in this mode is simlar to single device mode. Data/signal
connections are shown in Figure 15 and timng is shown in Figure10. In
this implementation, these are separate
ENR
signals. With SOCR and
ENR
inactive and no current cell transfer, asserting
ENR
notifies each
device the current word is an address. For selected devices, those with
cell space available in all FIFOs have a HIGH CLAVR. If one or more
selected FIFOs in a given UtopiaFIFO do not have room CLAVR is set
LOW.
As shown in Figure 10, and described above, continuous cell transfer
can occur with the same combination of FIFO destinations. With a change
in FIFO destinations, only a mnimumof one cycle delay will occur.
OUT-BAND ROUTING
SINGLE DEVICE DESTINATION (NO MULTICAST)
Configuration:
RMS =
“
0
”
indicates out-band routing.
MAS =
“
0
”
indicates no multicast mode.
BSS =
“
0
”
18 bit operation
To select fromup to eight UtopiaFIFOs, connect address/data lines as
shown in Figure 16. There is one
ENR
and multiple CLAVR signals (one
per each UtopiaFIFO). The address bus is common to all UtopiaFIFOs.
The timng is the same as in Figure 11. Once the current cell transfer is
completed, a new
ENR
signal and address will switch data transfer to the
new destination. By changing destinations, there is a one cycle delay as
ENR
must be de-asserted to select the new location. The address is
loaded on a de-asserted
ENR
signal. If the selected device has space
for an entire cell, it asserts CLAVR HIGH. All non-selected devices CLAVR
signals are tri-stated. When the selected FIFO has a complete cell
available, the asserted CLAVR informs the upstreamsystemit can send
data. On the next clock cycle,
ENR
asserts and data is placed on the data
bus and SOCR is asserted for the first word of data.
“
Polling
”
of new address locations can occur during the current cell
transfer. However, only one Utopia FIFO device can be polled at a time
as the address bus is common to all devices. To
“
poll
”
non-selected devices
will require separate
ENR
signals (one per Utopia FIFO) as well as
separate CLAVR lines to the switch.
MULTICAST OPERATION
Configuration:
RMS =
“
0
”
indicates out-band routing.
MAS =
“
1
”
indicates multicast mode.
BSS =
“
0
”
18 bit operation
In this case any combination of the four output FIFOs can receive the
same cell and the combination can vary among the individual Utopia
devices. Figure 17 shows the data/address connections. In this mode
RMS and MAS are both set LOW. The timng is the same for the single
device implementation. Each UtopiaFIFO, in turn, has the FIFO multicast
destination(s) loaded in the address registers; the CLAVR signal is
evaluated for cell availability. Once all desired location CLAVR signals are
known and all locations are available, the switch can send data to all
UtopiaFIFOs. Data is transferred upon assertion of
ENR
(only to those
selected devices) and SOCR with the data on the address bus. At the end
of a given cell transfer, if the same set of destinations are used, continuous
transfer with no latency, can take place. For a new set of cell destinations,
there is a one cycle delay for each selected UtopiaFIFO; if for example,
four of the eight devices involve cell destinations, each device must be
programmed separately. A set of address enables are loaded into each
device on a asserted
ENR
value. Each device evaluates the availability
of the selected FIFO(s) and sends an appropriate CLAVR signal.
Polling of all UtopiaFIFOs (both selected and non-selected) during cell
transfer can take place. For those non-selected UtopiaFIFOs, a LOW
ENR
signal with a new address combination, with SOCR LOW will be
evaluated and CLAVR set accordingly. As a current cell transfer is taking
place, no new asserted SOCR (common to all devices) will occur. The
absence of a HIGH SOCR notifies the device not to load data. For the
currently selected UtopiaFIFOs, if the address is changed to poll a new
combination, the current cell
destination(s) will not be altered. If the next cell destination(s) are the
same as the current one, this polling address will not change these
destination(s); thus, continuous cell transfer can still occur despite the on-
going polling.
BUILDING BLOCK IMPLEMENTATION:
36-BIT INPUT BUS
Input data buses greater than 18-bits can be utilized with the UtopiaFIFO.
Figure 18 shows how to direct a 36-bit bus to multiple UtopiaFIFOs
(multicast mode). For each of the UtopiaFIFO destinations, two devices are
used. The 36-bit bus is split up into 8 4-bit streams plus parity bits. As shown
in Figure 20, the data bits D0-D3 remain in these positions. Data bits D4-
D7 become D18-21, parity bit D8 remains in D8, etc. The
“
new
”
bits D0-
D17 are directed to the UtopiaFIFO
“
Bank A
”
which is set as a master. The
“
new
”
bits D18-D35 are directed to the UtopiaFIFO
“
Bank B
”
which is set
as a slave. This rearranging of data assures that upon reading of the output
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT77301L12PF | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77301L12PFI | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| IDT77305 | UTOPIAFIFO 4 PORT MULTIPLEXER FIFO |
| IDT77911 | Octal Transceivers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| IDT77914 | NICStAR⑩ Reference Design 155Mbps Network Interface Card NIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT77V011L155DA | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| IDT77V011L155DA8 | 功能描述:INTERFACE DPI-UTOPIA 144-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 專用 系列:- 標(biāo)準(zhǔn)包裝:3,000 系列:- 應(yīng)用:PDA，便攜式音頻/視頻，智能電話 接口:I²C，2 線串口 電源電壓:1.65 V ~ 3.6 V 封裝/外殼:24-WQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-QFN 裸露焊盤（4x4） 包裝:帶卷 (TR) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:1015 (CN2011-ZH PDF) 其它名稱:296-25223-2 |
| IDT77V106L25TF | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT77V106-L25TFI | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET TRANSCEIVER, 64 Pin, Plastic, QFP |
| IDT77V252L155PG | 制造商:Integrated Device Technology Inc 功能描述:ATM/SONET SEGMENTATION AND REASSEMBLY CIRCUIT, 208 Pin, Plastic, QFP |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。