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參數(shù)資料
| 型號： | IDT77301 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 8 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 21/29頁 |
| 文件大小： | 342K |
| 代理商： | IDT77301 |
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21
IDT77301
UtopiaFIFO
1 to 4 (128 x 9 x 4) Demultiplexer-FIFO Commercial and Industrial Temperature Ranges
data that the data will be in order. The SOCR signal is directed to all
UtopiaFIFOs and there are separate
ENR
and CLAVR signals for each
pair of UtopiaFIFOs. For a singlecast destination, the implementations can
be simplified (Figure 20). Here only one
ENR
is used and all CLAVR
signals tied together with a pull down register.
Upon writing the 36-bit data bus into the two banks of UtopiaFIFOs,
the first byte of the cell will load its lower bits to the master (low nibble position)
and the upper bits into the slave (lower nibble position). On the same cycle
the second byte of data will load in the same way except the nibbles will
be placed in the high nibble positions. The first and second bytes parity
bit is also written. Still on the same cycle, this procedure is repeated for the
third and forth bytes (and their respective parity bits).
To read data fromthe two banks of UtopiaFIFOs, one device is set as
the Master (MSE HIGH) and the other bank is set as a slave (MSE LOW).
The output fromeach device is set to
“
nibble mode
”
by setting BNE LOW.
The 8-bit output bus sent to the downstreamsystem(Utopia Level I
compliant) is composed of a 4-bit
“
nibble
”
(Q0-3) fromeach bank plus the
“
optional
”
parity (Q8) bit (see Figure 21). The output data bits Q4-6 are
left open. The Q7 data bit fromeach of the master device output FIFOs is
an output which feeds into the respective slave FIFO
’
s
ENS
signal (which
in slave mode is an input signal). The CLAVS signal fromthe downstream
systemis directed to both master and slave devices. The
ENS
and SOCS
fromthe master device are outputs to the downstreamsystem The SOCS
fromthe slave is left open.
With this configuration, output data fromboth UtopiaFIFOs will be
synchronized. Figure 22 shows the output timng. Once the downstream
systemcan accept a complete cell, CLAVS is asserted to both master
and slave devices. The master device recognizes CLAVS and once it
has a complete cell available to send, it asserts Q7 LOW. Q7 (master) is
feed into the slave
ENS
pin; only in the slave mode is the
ENS
an input.
The master device will wait one clock cycle, then asserts
ENS
and loads
the first nibble in Q0-3. SOCS (master) is asserted during this first
data nibble of the cell. The slave, recognizes a HIGH Q7 fromthe master,
and loads its first nibble of data on the next clock cycle. The
“
optional
”
parity
bit (Q8) will be placed on Q8 in an alternating fashion starting with the
master. The use of an external quick switch will prevent Q8 bus
contention between master and slave. The Q7 bit and
ENS
signal from
the master will stay asserted during the transfer of the current cell. Nibbles
fromboth devices are placed on the data bus. The parity bit alternates
between the two devices until cell transfer completion.
Once cell transfer is complete, a new cell, if available, can be transferred
in a continuous fashion. For this constant transfer of data, the CLAVS signal
must be asserted no later than the second to last byte to be read. The
CLAVS will be evaluated at this point; if HIGH, the master will determne
if a second complete cell is available. If a complete cell is present, Q7
(master) will remain LOW and on the following cycle will place data on the
Q0-3 data bus with
ENS
asserted and SOCS HIGH for the first nibble.
The slave will evaluate Q7 (master) and place the first nibble of the second
cell on the bus on the following cycle.
Once CLAVS is HIGH,
ENS
(master) will not de-assert until a
given cell is transferred.
ENS
will remain asserted until either no new
asserted CLAVS signal or no new complete cell available. During a cell
transfer and prior to the second to last byte transfer, the CLAVS signal is
a don
’
t care.
For input buses larger than 32-bit, multiple banks of UtopiaFIFO
s can be utilized. For a 64-bit input bus, one device is set as a master and
three set as slaves with the appropriate direction of the data bus on the input
side. The UtopiaFIFOs have the current drive capabilities to drive several
slave devices.
CELL LENGTH ERROR RECOVERY
After the start of cell signal (SOCR) is received, future SOCR assertions
prior to the end of current cell transfers are ignored. A counter keeps track
of byte transfers. If a
“
short cell
”
occurs (where a SOCR signal is received
prior to the end of cell transfer) the new SOCR is ignored and the data from
the next incomng cell is loaded into the existing
“
short cell
”
until it is filled
to normal cell size. Any additional bytes fromthe incomng cell are ignored.
The short cell is padded by the data fromthe second cell and the remainder
of the second cell is discarded. Recovery occurs on the third incomng cell.
If a
“
long cell
”
occurs (where the number of bytes exceeds the defined cell
size and no new SOCR signal received indicating a new cell) the extra
bytes are ignored by the UtopiaFIFO . The FIFO receiving the long cell
will wait for a new SOCR (and assertion of
ENR
and CLAVR) before
continuing data transfer.
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