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參數(shù)資料
| 型號： | IDT77301 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | UTOPIAFIFO 1 TO 4 (128 x 9 x 4) DEMULTIPLEXER-FIFO |
| 中文描述： | 128 X 9 OTHER FIFO, 8 ns, PQFP100 |
| 封裝： | 14 X 14 MM, 1.40 MM HEIGHT, TQFP-100 |
| 文件頁數(shù)： | 8/29頁 |
| 文件大?。?/td> | 342K |
| 代理商： | IDT77301 |
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IDT77301
UtopiaFIFO 1 to 4 (128 x 9 x 4) Demultiplexer-FIFO Commercial and Industrial Temperature Ranges
8
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Selection of a particular implementation for the input port and output
ports are easily made by configuring the following signals:
INPUT PORT CONFIGURATION
RMS (Routing Method Select)
“
1
”
in band routing;
“
0
”
out band routing
MAS (Multicast Address Select)
“
1
”
enable multicast;
“
0
”
enable
single cast
BSS (Bus Size Select)
“
1
”
enable 9-bit bus;
“
0
”
enable 18-bit bus
OUTPUT PORT CONFIGURATION
MSE (Master/Slave Enable)
“
1
”
enable master mode;
“
0
”
enable
slave mode
BNE (Byte/Nibble Enable)
“
1
”
enable byte mode;
”
0
”
enable
nibble mode
ROUTING METHOD SELECT (RMS)
The output FIFO cell destination is set with the Routing Method Select
(RMS) pin to either in-band or out-band routing. When using in-band
routing (RMS=1), refer to Figure 2a, the first 9 or 18-bit word, indicated
by SOCR, contains the 4-bit address of the output FIFO port. When using
out-band routing (RMS=0), refer to Figure 2b, a 5-bit output FIFO port
address is placed on the ADR(4:0) address bus. In both cases, the
address is loaded into the 77301 on its ADR(4:0) address bus.
MULTICAST/ADDRESS SELECT (MAS)
The Multicast/Address Select (MAS) pin determnes which routing
method is to be used. In Multicast mode (MAS=1) an incomng cell can be
sent to any combination of output FIFO port(s). When using out-band
routing (RMS=0) the 4-bit output FIFO address is placed directly on the
ADR(3:0) bus. Address line ADR4 is not used. Multicast output FIFO
address selection is described in Table 1b.
In Singlecast mode (MAS=0) an incomng cell can be sent to one output
FIFO port. The first two bits, ADR0 and ADR1, select the output FIFO port,
while the upper three bits ADR2, ADR3 and ADR4 select the appropriate
77301 according to its Device ID. ADR(4:0) equal to 11111 is reserved
for a Null PHY port. No PHY port will respond to this address. Refer to Table
1b for output FIFO address selection.
SCLK (I)
(I)
3240 drw 03
SDI (I)
Device ID
Cell_ Size
Cell_Size (0)
t
SLES
t
SLEH
t
DS
t
DH
Cell_Size (1)
Cell_Size (2)
Cell_Size (3)
Cell_Size (4)
Cell_Size (5)
Cell_Size (6)
ID (0)
ID (1)
ID (2)
Figure 1: Serial Loading of Cell Size and Device ID (x18 bit Mode)
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Device ID
ADR(4:0)
FIFO port
ADR(4:0)
0
000xx
A
xxx00
1
001xx
B
xxx01
2
010xx
C
xxx10
3
011xx
D
xxx11
4
100xx
5
101xx
x = Don't Care
6
110xx
7
111xx
3240 tbl 10
FIFO(s) Selected
ADR3
ADR2
ADR1
ADR0
No Selection
0
0
0
0
A
0
0
0
1
B
0
0
1
0
C
0
1
0
0
D
1
0
0
0
A,B
0
0
1
1
A,C
0
1
0
1
A,D
1
0
0
1
B,C
0
1
1
0
B,D
1
0
1
0
C,D
1
1
0
0
A,B,C
0
1
1
1
A,B,D
1
0
1
1
A,C,D
1
1
0
1
B,C,D
1
1
1
0
A,B,C,D
1
1
1
1
3240 tbl 11
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