參數(shù)資料
型號(hào): IDT82P2828BHG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 118/154頁(yè)
文件大小: 0K
描述: IC LIU T1/J1/E1 28+1CH 640-PBGA
標(biāo)準(zhǔn)包裝: 5
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 640-PBGA-EP(31x31)
包裝: 托盤
其它名稱: 82P2828BHG
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IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
66
February 6, 2009
3.6.2.6 Cascading Recovered Clocks of Multiple Devices
With the provided external CLKA and CLKB reference inputs for the
recovered clock outputs REFA and REFB, cascading of recovered
clocks between multiple devices can be implemented to provide a single
reference clock output from multiple devices without any additional
external logic. This can be useful in applications such as optical multi-
plexers where three IDT82P2828 are used in parallel to provide an inter-
face for up 84 T1 links for tributary aggregation to OC-3 line rates. Refer
In this setup, any two out of the 84 links can be selected to provide a
recovered clock output on REFA and REFB of device 3.
For example if it is required to recover link 1 [from device 1] for REFA
and link 80 [from device 3] for REFB, the register settings are as follows:
For REFA:
[device 1] set the REFA[4:0] bits (b4~0,REFA) to ‘00001’ to select
recovered clock of link1 as the clock source REFA1.
[device 2] set the REFA[4:0] bits (b4~0,REFA) to any value from
‘11101’ to ‘11111’ to select CLKA2 as the clock source for REFA2.
[device 3] set the REFA[4:0] bits (b4~0,REFA) to any value from
‘11101’ to ‘11111’ to select CLKA3 as the clock source for FEFA3.
For REFB:
[device3] set the REFB[4:0] bits (b4~0,REFA) to ‘11000’ to select
recovered clock of link80 as the clock source for REFB3.
Figure-44 Three IDT82P2828 in Parallel
RCLK28
REFA2
CLKA3
RCLK1
Device 2
Link58
Link29
REFB2
CLKB3
RCLK28
REFA3
RCLK1
Device 3
Link84
Link59
REFB3
RCLK28
REFA1
CLKA2
RCLK1
Link28
Link1
REFB1
CLKB2
CLKA1
CLKB1
Device 1
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