- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1924 > IDT82P2828BHG (IDT, Integrated Device Technology Inc)IC LIU T1/J1/E1 28+1CH 640-PBGA PDF資料下載
參數(shù)資料
| 型號： | IDT82P2828BHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 69/154頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 標(biāo)準(zhǔn)包裝： | 5 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2828BHG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁當(dāng)前第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Pin Description
21
February 6, 2009
TDn / TDPn
(n=0~28)
Input
AG8, AC1, AD3, AF1, AG2, AJ4,
AG5, AJ7, AJ19, AG20, AJ22,
AG23, AJ25, AG26, AJ28, D27,
B25, D24, B22, D21, B19, D18,
B16, A14, C13, A11, C10, A8, C7
TDn: Transmit Data for Channel 0 ~ 28
When the transmit system interface is configured to Single Rail NRZ Format mode, this multi-
plex pin is used as TDn.
TDn accepts Single Rail NRZ data. The data is sampled into the device on the active edge of
TCLKn.
The active level on TDn is selected by the TD_INV bit (b3, TCF1,...).
TDPn: Positive Transmit Data for Channel 0 ~ 28
When the transmit system interface is configured to Dual Rail NRZ Format mode or Dual Rail
RZ Format mode, this multiplex pin is used as TDPn.
In Transmit Dual Rail NRZ Format mode, the pre-encoded NRZ data is input on TDPn and
TDNn and sampled on the active edge of TCLKn.
In Transmit Dual Rail RZ Format mode, the pre-encoded RZ data is input on TDPn and TDNn.
The line code is as follows (when the TD_INV bit (b3, TCF1,...) is ‘0’):
The active level on TDPn and TDNn is selected by the TD_INV bit (b3, TCF1,...).
TDNn / TMFn
(n=0~28)
Input / Output AK9, AC2, AD4, AF2, AK3, AH4,
AK6, AH7, AH19, AK21, AH22,
AK24, AH25, AK27, AH28, C27,
A25, C24, A22, C21, A19, C18,
A16, D15, B13, D12, B10, D9, B7
TDNn: Negative Transmit Data for Channel 0 ~ 28
When the transmit system interface is configured to Dual Rail NRZ Format mode, this multi-
plex pin is used as TDNn.
(Refer to the description of TDPn for details).
TMFn: Transmit Multiplex Function for Channel 0 ~ 28
When the transmit system interface is configured to Single Rail NRZ Format mode or Dual
Rail RZ Format mode, this multiplex pin is used as TMFn.
TMFn is configured by the TMF_DEF[2:0] bits (b7~5, TCF1,...) and can indicate PRBS/ARB,
SAIS, TOC, TLOS, SEXZ, SBPV, SEXZ+SBPV, SLOS. Refer to Section 3.5.7.2 TMFn Indica-
tion for details.
The output on TMFn is updated on the active edge of TCLKn (if available). The active level of
TMFn is always high.
TCLKn / TDNn
(n=0~28)
Input
AJ9, AC3, AE1, AF3, AJ3, AG4,
AJ6, AG7, AG19, AJ21, AG22,
AJ24, AG25, AJ27, AG28, B27,
D26, B24, D23, B21, D20, B18,
D17, C15, A13, C12, A10, C9, A7
TCLKn: Transmit Clock for Channel 0 ~ 28
When the transmit system interface is configured to Single Rail NRZ Format mode or Dual
Rail NRZ Format mode, this multiplex pin is used as TCLKn.
TCLKn inputs a 1.544 MHz (in T1/J1 mode) or 2.048 MHz (in E1 mode) clock.
The data input on TDn (in Transmit Single Rail NRZ Format mode) or TDPn/TDNn (in Trans-
mit Dual Rail NRZ Format mode) is sampled on the active edge of TCLKn. The data output on
TMFn (in Transmit Single Rail NRZ Format mode) is updated on the active edge of TCLKn.
The active edge is selected by the TCK_ES bit (b4, TCF1,...).
TDNn: Negative Transmit Data for Channel 0 ~ 28
When the transmit system interface is configured to Dual Rail RZ Format mode, this multiplex
pin is used as TDNn.
(Refer to the description of TDPn for details).
Name
I / O
Pin No.
Description
TDPn
TDNn
Output Pulse on TTIPn Output Pulse on TRINGn *
0
Space
0
1
Negative Pulse
Positive Pulse
1
0
Positive Pulse
Negative Pulse
1
Space
Note:
* For Transmit Single Ended line interface, TRINGn should be open.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82P2916BFG | IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088BBG | IC LIU T1/E1/J1 OCTAL 256PBGA |
| IDT82V2041EPPG | IC LIU T1/J1/E1 1CH 44-TQFP |
| IDT82V2042EPFG | IC LIU T1/J1/E1 2CH SHORT 80TQFP |
| IDT82V2044EPFG | IC LIU T1/E1 QUAD SHORT 128-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2916 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2916BFG | 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| IDT82P2916BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
| IDT82P5088BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。