- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1924 > IDT82P2828BHG (IDT, Integrated Device Technology Inc)IC LIU T1/J1/E1 28+1CH 640-PBGA PDF資料下載
參數(shù)資料
| 型號(hào)： | IDT82P2828BHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 84/154頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC LIU T1/J1/E1 28+1CH 640-PBGA |
| 標(biāo)準(zhǔn)包裝： | 5 |
| 類型： | 線路接口裝置（LIU） |
| 規(guī)程： | E1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 640-BGA 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 640-PBGA-EP（31x31） |
| 包裝： | 托盤 |
| 其它名稱： | 82P2828BHG |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)當(dāng)前第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Functional Description
35
February 6, 2009
3.3.2
TX CLOCK RECOVERY
The Tx Clock Recovery is used only when the transmit system inter-
face is in Dual Rail RZ Format mode. When the transmit system inter-
face is in other modes, the Tx Clock Recovery is bypassed
automatically.
The Tx Clock Recovery is used to recover the clock signal from the
data input on TDPn and TDNn.
3.3.3
ENCODER
The Encoder is used only when the transmit system interface is in
Single Rail NRZ Format mode. When the transmit system interface is in
other modes, the Encoder is bypassed automatically.
In T1/J1 mode, the data to be transmitted is encoded by AMI or
B8ZS line code rule. In E1 mode, the data to be transmitted is encoded
by AMI or HDB3 line code rule. The line code rule is selected by the
T_CODE bit (b2, TCF1,...).
3.3.4
WAVEFORM SHAPER
The IDT82P2828 provides two ways to manipulate the pulse shape
before data is transmitted:
Preset Waveform Template;
User-Programmable Arbitrary Waveform.
3.3.4.1 Preset Waveform Template
In T1/J1 applications, the waveform template meets T1.102. The T1
template is shown in Figure-15. It is measured in the far end, as shown
in Figure-16. The J1 template is measured in the near end line side.
In T1 applications, to meet the template, five preset waveform
templates are provided according to five grades of cable length. The
selection is made by the PULS[3:0] bits (b3~0, PULS,...). In J1 applica-
tions, the PULS[3:0] bits (b3~0, PULS,...) should be set to ‘0111’. Refer
to Table-5 for details.
Figure-15 DSX-1 Waveform Template
Figure-16 T1 Waveform Template Measurement Circuit
Table-4 Multiplex Pin Used in Transmit System Interface
Transmit System
Interface
Multiplex Pin Used On Transmit System
Interface
TDn / TDPn
TDNn / TMFn
TCLKn / TDNn
Single Rail NRZ Format
TDn 1
TMFn 2
TCLKn 3
Dual Rail NRZ Format
TDPn 1
TDNn 1
TCLKn 3
Dual Rail RZ Format
TDPn 1
TMFn 2
TDNn 1
Note:
1. The active level on TDn, TDPn and TDNn is selected by the TD_INV bit (b3,
2. TMFn is always active high.
3. The active edge of TCLKn is selected by the TCK_ES bit (b4, TCF1,...). If TCLKn is
missing, i.e., no transition for more than 64 T1/E1 clock cycles, the TCKLOS_S bit (b3,
STAT0,...) will be set. A transition from ‘0’ to ‘1’ on the TCKLOS_S bit (b3, STAT0,...) or
any transition (from ‘0’ to ‘1’ or from ‘1’ to ‘0’) on the TCKLOS_S bit (b3, STAT0,...) will
set the TCKLOS_IS bit (b3, INTS0,...) to ‘1’, as selected by the TCKLOS_IES bit (b3,
INTES,...). When the TCKLOS_IS bit (b3, INTS0,...) is ‘1’, an interrupt will be reported
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
1.2
0
250
500
750
1000
1250
Time (ns)
Nor
m
al
iz
ed
Ampl
itude
IDT82P2828
TTIPn
TRINGn
Cable
RLOAD VOUT
Note: RLOAD = 100
+ 5%
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT82P2916BFG | IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088BBG | IC LIU T1/E1/J1 OCTAL 256PBGA |
| IDT82V2041EPPG | IC LIU T1/J1/E1 1CH 44-TQFP |
| IDT82V2042EPFG | IC LIU T1/J1/E1 2CH SHORT 80TQFP |
| IDT82V2044EPFG | IC LIU T1/E1 QUAD SHORT 128-TQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82P2916 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:16-Channel High-Density T1/E1/J1 Line Interface Unit |
| IDT82P2916BFG | 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA RoHS:是 類別:集成電路 (IC) >> 接口 - 電信 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS 產(chǎn)品變化通告:Product Discontinuation 06/Feb/2012 標(biāo)準(zhǔn)包裝:750 系列:* |
| IDT82P2916BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 16CH SH 484BGA |
| IDT82P5088 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
| IDT82P5088BBBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:Universal Octal T1/E1/J1 LIU with Integrated Clock Adapter |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。