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參數(shù)資料
型號： IDT82P2828BHG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 154/154頁
文件大?。?/td> 0K
描述： IC LIU T1/J1/E1 28+1CH 640-PBGA
標(biāo)準(zhǔn)包裝： 5
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 640-BGA 裸露焊盤
供應(yīng)商設(shè)備封裝： 640-PBGA-EP（31x31）
包裝： 托盤
其它名稱： 82P2828BHG
IDT82P2828
28(+1) CHANNEL HIGH-DENSITY T1/E1/J1 LINE INTERFACE UNIT
Programming Information
99
February 6, 2009
LOS - LOS Configuration Register
Address: 00DH, 04DH, 08DH, 0CDH, 10DH, 14DH, 18DH, 1CDH, (CH1~CH8)
20DH, 24DH, 28DH, 2CDH, 30DH, 34DH, 38DH, 3CDH, (CH9~CH16)
40DH, 44DH, 48DH, 4CDH, 50DH, 54DH, 58DH, 5CDH, (CH17~CH24)
60DH, 64DH, 68DH, 6CDH, (CH25~CH28)
7CDH (CH0)
Type: Read / Write
Default Value: 15H
Bit
Name
Description
7
LAC
This bit selects the LLOS, SLOS and AIS criteria.
0: T1.231 (in T1/J1 mode) / G.775 (in E1 mode). (default)
1: I.431 (in T1/J1 mode) / ETSI 300233 & I.431 (in E1 mode).
6 - 4
ALOS[2:0]
These bits select the amplitude threshold (Q). When the amplitude of the data is less than Q Vpp for N consecutive pulse inter-
vals, LLOS is declared. The consecutive pulse intervals (N) are determined by the LAC bit (b7, LOS,...).
The ALOS[2:0] settings for Normal Receive mode and Line Monitor mode are different. Refer to below tables.
765
43
21
0
LAC
ALOS2
ALOS1
ALOS0
TALOS1
TALOS0
TDLOS1
TDLOS0
ALOS[2:0] Setting in Normal Receive Mode
ALOS[2:0]
Q (Vpp)
vs. 6.0 Vpp (dB)
vs. 4.74 Vpp (dB)
000
0.5
21.58
19.54
001 (default)
0.7
18.66
16.61
010
0.9
16.48
14.43
011
1.2
13.98
11.93
100
1.4
12.64
10.59
101
1.6
11.48
9.43
110
1.8
10.46
8.41
111
2.0
9.54
7.49
ALOS[2:0] Setting in Line Monitor Mode
ALOS[2:0]
Q (Vpp)
vs. 6.0 Vpp (dB)
vs. 4.74 Vpp (dB)
000
1.0
15.56
13.52
001 (default)
1.4
12.64
10.59
010
1.8
10.46
8.41
011
2.2
8.71
6.67
1xx
reserved.
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