Figure-17 Remote Loopback 3.8.4" />
參數(shù)資料
型號： IDT82V2082BFG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 31/88頁
文件大?。?/td> 0K
描述： IC LIU T1/E1/J1 2CH 81BGA
標準包裝： 360
類型： 線路接口裝置（LIU）
規(guī)程： T1，E1，J1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 81-LFBGA
供應商設備封裝： 81-CABGA（8x8）
包裝： 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
37
May 4, 2009
Figure-17 Remote Loopback
3.8.4
INBAND LOOPBACK
When PATT[1:0] bits (MAINT0, 0CH...) are set to ‘11’, the correspond-
ing channel is configured in Inband Loopback mode. In this mode, an
unframed activate/Deactivate Loopback Code is generated repeatedly in
transmit direction per ANSI T1. 403 which overwrite the transmit signals.
In receive direction, the framed or unframed code is detected per ANSI T1.
403, even in the presence of 10-2 bit error rate.
If the Automatic Remote Loopback is enabled by setting ARLP bit
(MAINT1, 0DH...) to ‘1’, the chip will establish/demolish the Remote Loop-
back based on the reception of the Activate Loopback Code/ Deactivate
Loopback Code for 5.1 s. If the ARLP bit (MAINT1, 0DH...) is set to ‘0’, the
Remote Loopback can also be demolished forcedly.
3.8.4.1 Transmit Activate/Deactivate Loopback Code
The pattern of the transmit Activate/Deactivate Loopback Code is
defined by the TIBLB[7:0] bits (MAINT3, 0FH...). Whether the code repre-
sentsanActivateLoopbackCodeoraDeactivateLoopbackCodeisjudged
by the far end receiver. The length of the pattern ranges from 5 bits to 8 bits,
as selected by the TIBLB_L[1:0] bits (MAINT2, 0EH...). The pattern can be
programmed to 6-bit-long or 8-bit-long respectively by repeating itself if it
is 3-bit-long or 4-bit-long. When the PATT[1:0] bits (MAINT0, 0CH...) are
set to ‘11’, the transmission of the Activate/Deactivate Loopback Code is
initiated. If the PATT_CLK bit (MAINT0, 0CH...) is set to ‘0’ and the
PATT[1:0]bits(MAINT0,0CH...)areset to‘00’,thetransmissionofthe Acti-
vate/Deactivate Loopback Code will stop.
The local transmit activate/deactivate code setting should be the same
as the receive code setting in the remote end. It is the same thing for the
other way round.
3.8.4.2 Receive Activate/Deactivate Loopback Code
The pattern of the receive Activate Loopback Code is defined by the
RIBLBA[7:0] bits (MAINT4, 10H...). The length of this pattern ranges from
5 bits to 8 bits, as selected by the RIBLBA_L [1:0] bits (MAINT2, 0EH...).
The pattern can be programmed to 6-bit-long or 8-bit-long respectively by
repeating itself if it is 3-bit-long or 4-bit-long.
The pattern of the receive Deactivate Loopback Code is defined by the
RIBLBD[7:0] bits (MAINT5, 11H...). The length of the receive Deactivate
Loopback Code ranges from 5 bits to 8 bits, as selected by the
RIBLBD_L[1:0] bits (MAINT2, 0EH...). The pattern can be programmed to
6-bit-long or 8-bit-long respectively by repeating itself if it is 3-bit-long or 4-
bit-long.
After the Activate Loopback Code has been detected in the receive data
for more than 30 ms (in E1 mode) / 40 ms (in T1/J1 mode), the IBLBA_S
bit (STAT0, 16H...) will be set to ‘1’ to declare the reception of the Activate
Loopback Code.
After the Deactivate Loopback Code has been detected in the receive
dataformorethan30ms(InE1mode)/40ms(InT1/J1mode),theIBLBD_S
bit(STAT0,16H...)willbesetto‘1’todeclarethereceptionoftheDeactivate
Loopback Code.
When the IBLBA_IES bit (INTES, 15H...) is set to ‘0’, only the ‘0’ to ‘1’
transitionof theIBLBA_S bitwillgeneratean interruptandset theIBLBA_IS
bit (INTS0, 18H...) to ‘1’. When the IBLBA_IES bit is set to ‘1’, any changes
of the IBLBA_S bit will generate an interrupt and set the IBLBA_IS bit
(INTS0, 18H...) to ‘1’. The IBLBA_IS bit will be reset to ‘0’ after being read.
When the IBLBD_IES bit (INTES, 15H...) is set to ‘0’, only the ‘0’ to ‘1’
transitionoftheIBLBD_SbitwillgenerateaninterruptandsettheIBLBD_IS
bit (INTS0, 18H...) to ‘1’. When the IBLBD_IES bit is set to ‘1’, any changes
of the IBLBD_S bit will generate an interrupt and set the IBLBD_IS bit
(INTS0, 18H...) to ‘1’. The IBLBD_IS bit will be reset to ‘0’ after being read.
B8ZS/
HDB3/AMI
Encoder
Jitter
Attenuator
B8ZS/
HDB3/AMI
Decoder
Jitter
Attenuator
Data
Slicer
Adaptive
Equalizer
LOS/AIS
Detection
Clock and
Data
Recovery
Receiver
Internal
Termination
TCLKn
TDNn
TDn/TDPn
RCLKn
CVn/RDNn
LOSn
RDn/RDPn
RRINGn
TTIPn
TRINGn
RTIPn
Remote
Loopback
Line
Driver
Waveform
Shaper/LBO
Transmitter
Internal
Termination
One of the Two Identical Channels
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相關代理商/技術參數(shù)
參數(shù)描述
IDT82V2082BFG8 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 2CH 81BGA
IDT82V2082BFGBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
IDT82V2082PF 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2082PF8 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 驅動器，接收器，收發(fā)器 系列:- 標準包裝:250 系列:- 類型:收發(fā)器 驅動器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR)
IDT82V2082PFBLANK 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
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