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參數(shù)資料
| 型號(hào)： | IDT82V2082BFG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 36/88頁(yè) |
| 文件大小： | 0K |
| 描述： | IC LIU T1/E1/J1 2CH 81BGA |
| 標(biāo)準(zhǔn)包裝： | 360 |
| 類(lèi)型： | 線路接口裝置（LIU） |
| 規(guī)程： | T1，E1，J1 |
| 電源電壓： | 3.13 V ~ 3.47 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 81-LFBGA |
| 供應(yīng)商設(shè)備封裝： | 81-CABGA（8x8） |
| 包裝： | 托盤(pán) |
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IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
41
May 4, 2009
3.11 MCLK AND TCLK
3.11.1 MASTER CLOCK (MCLK)
MCLK is an independent, free-running reference clock. MCLK is 1.544
MHzforT1/J1applicationsand2.048MHzinE1mode.Thisreferenceclock
is used to generate several internal reference signals:
Timing reference for the integrated clock recovery unit.
Timing reference for the integrated digital jitter attenuator.
Timing reference for microcontroller interface.
Generation of RCLK signal during a loss of signal condition if AIS is
enabled.
Reference clock during Transmit All Ones (TAOS), all zeros, PRBS/
QRSS and Inband Loopback code if it is selected as the reference
clock. For ATAO and AIS, MCLK is always used as the reference
clock.
Reference clock during Transmit All Ones (TAO) condition or send-
ing PRBS/QRSS in hardware control mode.
Figure-20 shows the chip operation status in different conditions of
MCLK and TCLKn. The missing of MCLK will set all the TTIPn/TRINGn to
high impedance state.
3.11.2 TRANSMIT CLOCK (TCLK)
TCLKn is used to sample the transmit data on TDn/TDPn, TDNn. The
active edge of TCLKn can be selected by the TCLK_SEL bit (TCF0, 04H...).
During Transmit All Ones, PRBS/QRSS patterns or Inband Loopback
Code, either TCLKn or MCLK can be used as the reference clock. This is
selected by the PATT_CLK bit (MAINT0, 0CH...).
But for Automatic Transmit All Ones and AIS, only MCLK is used as the
reference clock and the PATT_CLK bit is ignored. In Automatic Transmit
All Ones condition, the ATAO bit (MAINT0, 0CH) is set to ‘1’. In AIS condi-
tion, the AISE bit (MAINT0, 0CH) is set to ‘1’.
If TCLKn has been missing for more than 70 MCLK cycles, TCLK_LOS
bit (STAT0, 16H...) will be set, and the corresponding TTIPn/TRINGn will
become high impedance if this channel is not used for remote loopback or
isnotusingMCLK totransmitinternal patterns (TAOS,AllZeros,PRBSand
in-band loopback code). When TCLK is detected again, TCLK_LOS bit
(STAT0, 16H...) will be cleared. The reference frequency to detect a TCLK
loss is derived from MCLK.
Figure-20 TCLK Operation Flowchart
both the transmitters high
impedance
yes
MCLK=H/L?
normal operation
Clocked
TCLKn status?
L/H
clocked
generate transmit clock loss
interrupt if not masked in
software control mode;
transmitter n high impedance
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V2082BFG8 | 制造商:Integrated Device Technology Inc 功能描述:IC LIU T1/E1/J1 2CH 81BGA |
| IDT82V2082BFGBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
| IDT82V2082PF | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PF8 | 功能描述:IC LIU T1/J1/E1 2CH 80-TQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 接口 - 驅(qū)動(dòng)器，接收器，收發(fā)器 系列:- 標(biāo)準(zhǔn)包裝:250 系列:- 類(lèi)型:收發(fā)器 驅(qū)動(dòng)器/接收器數(shù):2/2 規(guī)程:RS232 電源電壓:3 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| IDT82V2082PFBLANK | 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT |
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