參數(shù)資料
型號: IDT82V2082BFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 28/88頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 2CH 81BGA
標(biāo)準(zhǔn)包裝: 360
類型: 線路接口裝置(LIU)
規(guī)程: T1,E1,J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 81-LFBGA
供應(yīng)商設(shè)備封裝: 81-CABGA(8x8)
包裝: 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
34
May 4, 2009
3.6.2
AIS DETECTION
The Alarm Indication Signal can be detected by the IDT82V2082 when
the Clock & Data Recovery unit is enabled. The status of AIS detection is
reflected in the AIS_S bit (STAT0, 16H...). In T1/J1 applications, the criteria
for declaring/clearing AIS detection are in compliance with the ANSI
T1.231. In E1 applications, the criteria for declaring/clearing AIS detection
comply with the ITU G.775 or the ETSI 300233, as selected by the LAC bit
(MAINT0, 0CH...). Table-19 summarizes different criteria for AIS detection
Declaring/Clearing.
Table-19 AIS Condition
ITU G.775 for E1
(LAC bit is set to ‘0’ by default)
ETSI 300233 for E1
(LAC bit is set to ‘1’)
ANSI T1.231 for T1/J1
AIS
detected
Less than 3 zeros contained in each of two consecutive
512-bit streams are received
Less than 3 zeros contained in a 512-bit
stream are received
Less than 9 zeros contained in an 8192-bit stream
(a ones density of 99.9% over a period of 5.3ms)
AIS
cleared
3 or more zeros contained in each of two consecutive
512-bit streams are received
3 or more zeros contained in a 512-bit
stream are received
9 or more zeros contained in an 8192-bit stream
are received
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