參數(shù)資料
型號(hào): IDT82V2082BFG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 18/88頁(yè)
文件大小: 0K
描述: IC LIU T1/E1/J1 2CH 81BGA
標(biāo)準(zhǔn)包裝: 360
類(lèi)型: 線路接口裝置(LIU)
規(guī)程: T1,E1,J1
電源電壓: 3.13 V ~ 3.47 V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 81-LFBGA
供應(yīng)商設(shè)備封裝: 81-CABGA(8x8)
包裝: 托盤(pán)
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
FUNCTIONAL DESCRIPTION
25
May 4, 2009
3.3.4
TRANSMIT PATH LINE INTERFACE
The transmit line interface consists of TTIPn and TRINGn pins. The
impedance matching can be realized by the internal impedance matching
circuit or the external impedance matching circuit. If T_TERM[2] is set to
‘0’, the internal impedance matching circuit will be selected. In this case,
the T_TERM[1:0] bits (TERM, 02H...) can be set to choose 75
, 100 ,
110
or 120 internal impedance of TTIPn/TRINGn. If T_TERM[2] is set
to ‘1’, the internal impedance matching circuit will be disabled. In this case,
the external impedance matching circuit will be used to realize the imped-
ance matching. For T1/J1 mode, the external impedance matching circuit
for the transmitter is not supported.
Figure-9 shows the appropriate external components to connect with
the cable for one channel. Table-14 is the list of the recommended imped-
ance matching for transmitter.
In hardware control mode, TERMn pin can be used to select impedance
matchingforbothreceiverandtransmitteronaperchannelbasis.IfTERMn
pin is low, internal impedance network will be used. If TERMn pin is high,
external impedance network will be used in E1 mode, or external imped-
ance network for receiver and internal impedance network for transmitter
will be used in T1/J1 mode. (This applies to ZB die revision only). When
internal impedance network is used, PULSn[3:0] pins should be set to
select the specific internal impedance in the corresponding channel. Refer
The TTIPn/TRINGn can also be turned into high impedance globally by
pulling THZ pin to high or individually by setting the THZ bit (TCF1, 05H...)
to ‘1’. In this state, the internal transmit circuits are still active.
In hardware control mode, TTIPn/TRINGn pins can be turned into high
impedance globally by pulling THZ pin to high. Refer to 5 HARDWARE CON-
for details.
Besides, in the following cases, TTIPn/TRINGn will also become high
impedance:
Loss of MCLK;
Loss of TCLKn (exceptions: Remote Loopback; Transmit internal
pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
Note: The precision of the resistors should be better than ± 1%
Table-13 Transmit Waveform Value For DS1 -22.5 dB LBO
Sample
UI 1
UI 2
UI 3
UI 4
1
0000000
0101100
0011110
0001000
2
0000000
0101110
0011100
0000111
3
0000000
0110000
0011010
0000110
4
0000000
0110001
0011000
0000101
5
0000001
0110010
0010111
0000101
6
0000011
0110010
0010101
0000100
7
0000111
0110010
0010100
0000100
8
0001011
0110001
0010011
0000011
9
0001111
0110000
0010001
0000011
10
0010101
0101110
0010000
0000010
11
0011001
0101100
0001111
0000010
12
0011100
0101001
0001110
0000010
13
0100000
0100111
0001101
0000001
14
0100011
0100100
0001100
0000001
15
0100111
0100010
0001010
0000001
16
0101010
0100000
0001001
0000001
SCAL[5:0] = 000100 (default), One step change of this value of SCAL[5:0]
results in 25% scaling up/down against the pulse amplitude.
Table-14 Impedance Matching for Transmitter
Cable Configuration
Internal Termination
External Termination
T_TERM[2:0]
PULS[3:0]
RT
T_TERM[2:0]
PULS[3:0]
RT
E1/75
000
0000
0
1XX
0001
9.4
E1/120
001
0001
T1/0~133 ft
010
0010
-
T1/133~266 ft
0011
T1/266~399 ft
0100
T1/399~533 ft
0101
T1/533~655 ft
0110
J1/0~655 ft
011
0111
0 dB LBO
010
1000
-7.5 dB LBO
1001
-15.0 dB LBO
1010
-22.5 dB LBO
1011
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