參數(shù)資料
型號(hào): IDT82V2082BFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 43/88頁
文件大?。?/td> 0K
描述: IC LIU T1/E1/J1 2CH 81BGA
標(biāo)準(zhǔn)包裝: 360
類型: 線路接口裝置(LIU)
規(guī)程: T1,E1,J1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 81-LFBGA
供應(yīng)商設(shè)備封裝: 81-CABGA(8x8)
包裝: 托盤
IDT82V2082
DUAL CHANNEL T1/E1/J1 LONG HAUL/SHORT HAUL LINE INTERFACE UNIT
PROGRAMMING INFORMATION
48
May 4, 2009
4.3.2
TRANSMIT AND RECEIVE TERMINATION REGISTER
4.3.3
JITTER ATTENUATION CONTROL REGISTER
Table-29 TERM: Transmit and Receive Termination Configuration Register
(R/W, Address = 02H, 22H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved.
T_TERM[2:0]
5-3
000
These bits select the internal termination for transmit line impedance matching.
= 000: Internal 75
impedance matching
= 001: Internal 120
impedance matching
= 010: Internal 100
impedance matching
= 011: Internal 110
impedance matching
= 1xx: Selects external impedance matching resistors for E1 mode only. T1/J1 does not require external impedance
resistors (see Table-14).
R_TERM[2:0]
2-0
000
These bits select the internal termination for receive line impedance matching.
= 000: Internal 75
impedance matching
= 001: Internal 120
impedance matching
= 010: Internal 100
impedance matching
= 011: Internal 110
impedance matching
= 1xx: Selects external impedance matching resistors (see Table-15).
Table-30 JACF: Jitter Attenuation Configuration Register
(R/W, Address = 03H, 23H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved.
JA_LIMIT
5
1
= 0: Normal mode
= 1: JA limit mode
JACF[1:0]
4-3
00
Jitter Attenuation configuration
= 00/10: JA not used
= 01: JA in transmit path
= 11: JA in receive path
JADP[1:0]
2-1
00
Jitter Attenuation depth select
= 00: 128 bits
= 01: 64 bits
= 1x: 32 bits
JABW
0
Jitter transfer function bandwidth select
= 0: 6.8 Hz (E1)
5 Hz (T1/J1)
= 1: 0.9 Hz (E1)
1.25 Hz (T1/J1)
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