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| 型號(hào)： | IDT82V2108PXG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 252/292頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 控制器類型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V2108PXG8 |
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
52
March 5, 2009
3.11.2.3
Receive Multiplexed Mode
In this mode (refer to Figure 19), two multiplexed buses are used to
receive the data from all eight framers. The data from up to four framers
is byte-interleaved output on one of the two multiplexed buses. The mul-
tiplexed bus is chosen by the MRBS (b7, T1/J1-003H). When the data
from four framers is output on one multiplexed bus, the sequence of
data is arranged by setting the channel offset TSOFF[6:0] (b6~0, T1/J1-
077H). The data from different framers on one multiplexed bus must be
shifted at a different channel offset to avoid data mixing. Then the
received data of each framer can be controlled by the MRBC (b6, T1/J1-
003H) to output to the selected multiplexed bus or not. The MRBC (b6,
T1/J1-003H) of the framers that are output to the same multiplexed bus
must be set to the same value.
In the Receive Multiplexed mode, the data on the system interface
is clocked by MRSCCK. The active edge of MRSCCK to sample the
pulse on MRSCFS and to update the data on MRSD, MRSFS and MRS-
SIG is determined by the following bits in the registers (refer to
In the Receive Multiplexed mode, the Multiplexed Receive Side
System Common Clock (MRSCCK) is provided by the system side. It is
used as a common timing clock for all eight framers. The frequency of
MRSCCK can be chosen by the CMS (b4, T1/J1-078H) to be the same
as the bit rate of the received data stream (8.192Mb/s), or double the bit
rate of the received data stream (16.384 Mb/s). If the frequency of
RSCCK is double the bit rate of the received data stream, there will be
two active edges in one bit duration. In this case, the
RSD_RSCFS_EDGE (b5, T1/J1-078H) determines the active edge to
update the signal on the MRSD, MRSSIG and MRSFS pins; however,
the pulse on MRSCFS is always sampled on its first active edge. If the
CMS (b4, T1/J1-078H) or the RSD_RSCFS_EDGE (b5, T1/J1-078H) of
any of the eight framers is configured as logic 1, all the others are taken
as logic 1. That is, the CMS (b4, T1/J1-078H) and the
RSD_RSCFS_EDGE (b5, T1/J1-078H) of the eight framers should be
configured to the same value in the Receive Multiplexed mode.
In the Receive Multiplexed mode, the Multiplexed Receive Side
System Common Frame Pulse (MRSCFS) is used as a common framing
signal to align the data streams on the two multiplexed buses. MRSCFS
is asserted on the F-bit. The valid polarity of MRSCFS is configured by
the FPINV (b6, T1/J1-078H). The FPINV (b6, T1/J1-078H) of the eight
framers should be set to the same value.
In the Receive Multiplexed mode, the bit rate on the MRSD pin is
8.192Mb/s.
In the Receive Multiplexed mode, regardless of the setting in the
RSFSP (b2, T1/J1-001H) and ALTIFP (b1, T1/J1-001H), MRSFS can
only indicate each F-bit of SF/ESF of the selected first framer. The valid
polarity of RSFSn is configured by the FPINV (b6, T1/J1-078H). The
FPINV (b6, T1/J1-078H) of the eight framers should be set to the same
value.
In the Receive Multiplexed mode, MRSSIG outputs extracted sig-
naling. The extracted signaling bits are channel aligned with the data
output on MRSD.
each channel is the first bit to be output.
Figure 33. T1/J1 Receive Multiplexed Mode - Functional Timing Example 1
Table 24: Active Edge Selection of MRSCCK (in T1/J1 Receive
Multiplexed Mode)
the Bit Determining the Active Edge of MRSCCK
MRSCFS
RSCFSFALL (b1, T1/J1-003H)
MRSFS
RSCCKRISE (b0, T1/J1-003H)
MRSD
MRSSIG
Note:
When the RSCFSFALL/RSCCKRISE of any of the eight framers is configured as logic 1,
all the others are taken as logic 1. That is, the RSCFSFALL/RSCCKRISE should be con-
figured to the same value in Receive Multiplexed mode.
It is a special case when the CMS (b4, T1/J1-078H) is logic 1 and the RSCFSFALL (b1,
T1/J1-003H) is not equal to RSCCKRISE (b0, T1/J1-003H). The RSD_RSCFS_EDGE
(b5, T1/J1-078H) is invalid and the signals on the MRSD, MRSSIG and the MRSFS pins
are updated on the first active edge of RSCCK.
F
Framer1_CH1
45
6
12
3
8
7
F
P
8
7
B
A
D
C
P
D
C
P
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
XX
X
MRSCCK
MRSCFS
MRSFS
MRSD
MRSSIG
The CMS (b4, T1/J1-078H) is logic 0, i.e., the bankplane clock rate is 8.192Mbit/s.
The RSCCKRISE(b0, T1/J1-003H) is logic 1 and the RSCFSFALL (b1, T1/J1-003H) is logic 0.
In this example, Framer1 to Frame4 are supposed to be multiplexed to one multiplexed bus.
When the TSOFF[6:0] of Framer1 are set to 7'b0000000, the TSOFF[6:0] of Framer2 are set to 7'b0000001, the TSOFF[6:0] of Framer3 are set to 7'b0000010, the TSOFF[6:0] of Framer4 are set to
7'b0000011, the BOFF_EN of the four Framers are set to logic 0:
F-bit
Parity
bit
Framer1
F-bit
Parity
bit
Framer2
F-bit
Parity
bit
Framer3
F-bit
Parity
bit
Framer4
(The 'X' represents the filled bits and has no meaning.)
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