參數(shù)資料
型號： IDT82V2616BBG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 28/99頁
文件大?。?/td> 0K
描述： IC INVERSE MUX 16CH ATM 272-PBGA
標(biāo)準包裝： 1
應(yīng)用： 無線
接口： Utopia
電源電壓： 2.97 V ~ 3.63 V
封裝/外殼： 260-BGA
供應(yīng)商設(shè)備封裝： 260-PBGA（19x19）
包裝： 托盤
安裝類型： 表面貼裝
其它名稱： 82V2616BBG
PROGRAMMING INFORMATION for IMAOS16
34
December 4, 2006
IDT82V2616
Inverse Multiplexing for ATM
5.3
COMMAND DESCRIPTION
Each command description contains two parts: Command Parame-
ters and Command Reply. In the Command Parameters part, a figure is
used to illustrate the byte sequence of the parameters. All the parameter
descriptions are listed below the figure. In the Command Reply part,
another figure is used to illustrate the reply sequence in the reply
message. The reply description is listed below the figure. For detailed
information about the packet of command message and reply message,
refer to page 32.
Table-17 ConfigDev Command (Encoding: 01H)
This is the first command to be issued. If this command is not issued, the default value will be used.
Command Parameters
Byte Sequence
Parameter Name
Default
Description
1-2
SysClk
4E20H
SysClk=Frequency of System Clock (Hz)/1000. For example, if the system clock is 20 MHz, this value
would be 20000.
Unit: sys-ticks in 1 ms (MSB first)
Note: Wrong configuration will make IMAOS’s timer work improperly.
3Tin
2H
Timer of entering failure alarm state. When a defect persists for a period set by this timer, the
IDT82V2616will enter failure alarm state.
Unit: 1 s
4Texit
0AH
Timer of exiting failure alarm state. If a defect no longer exists for a period set by this timer, the
IDT82V2616 will exit failure alarm state.
Unit: 1 s
5
No
0H
Reserved. Write 0 to this field.
6
TCWorkMode
7H
7
TCAlpha&Delta
67H
Alpha value is the number of consecutive incorrect HEC fields for the Rx cell synchronization state
machine to exit sync state.
Delta value is the number of consecutive correct HEC fields for the Rx cell synchronization state machine
to enter sync state.
1-2
34567
8
SysClk
Tin
Texit
No
TCWorkMode
TCAlpha&Delta
TCLCD_Threshold
Bit Position
Description
7~3
Don’t Care
2
1: Enable Tx TC scrambling (default);
0: Disable Tx TC scrambling
1
1: Enable Rx TC HEC error correct control (default);
0: Disable Rx TC HEC error correct control
0
1: Enable Rx TC de-scrambling (default);
0: Disable Rx TC de-scrambling
Bit Position
Description
7-4
Delta value. Valid is 0~15.
3-0
Alpha value. Valid is 0~15.
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