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參數(shù)資料
| 型號： | IDT82V3280EQG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 101/171頁 |
| 文件大小： | 0K |
| 描述： | IC PLL WAN SE STRATUM 2 100TQFP |
| 標準包裝： | 90 |
| 類型： | 時鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，PECL |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 14:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤 |
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IDT82V3280
WAN PLL
Functional Description
35
December 9, 2008
phase locked to any input clock. The frequency offset acquiring method
is selected by the MAN_HOLDOVER bit, the AUTO_AVG bit and the
FAST_AVG bit, as shown in Table 19:
3.10.1.5.1 Automatic Instantaneous
By this method, the T0 DPLL freezes at the operating frequency
when it enters Holdover mode. The accuracy is 4.4X10-8 ppm.
3.10.1.5.2 Automatic Slow Averaged
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 110 minutes. The accuracy is
1.1X10-5 ppm.
3.10.1.5.3 Automatic Fast Averaged
By this method, an internal IIR (Infinite Impulse Response) filter is
employed to get the frequency offset. The IIR filter gives a 3 dB attenua-
tion point corresponding to a period of 8 minutes. The accuracy is
1.1X10-5 ppm.
3.10.1.5.4 Manual
By this method, the frequency offset is set by the
T0_HOLDOVER_FREQ[23:0] bits. The accuracy is 1.1X10-5 ppm.
The frequency offset of the T0 DPLL output is indicated by the
CURRENT_DPLL_FREQ[23:0] bits.
The device provides a reference for the value to be written to the
T0_HOLDOVER_FREQ[23:0] bits. The value to be written can refer to
the value read from the CURRENT_DPLL_FREQ[23:0] bits or the
T0_HOLDOVER_FREQ[23:0] bits (refer to Chapter 3.10.1.5.5 Holdover
Frequency Offset Read); or then be processed by external software fil-
tering.
3.10.1.5.5 Holdover Frequency Offset Read
The offset value, which is acquired by Automatic Slow Averaged,
Automatic Fast Averaged and is set by related register bits, can be read
from the T0_HOLDOVER_FREQ[23:0] bits by setting the READ_AVG
bit and the FAST_AVG bit, as shown in Table 20.
The frequency offset in ppm is calculated as follows:
Holdover Frequency Offset (ppm) = T0_HOLDOVER_FREQ[23:0] X
0.000011
3.10.1.6
Pre-Locked2 Mode
In Pre-Locked2 mode, the T0 DPLL output attempts to track the
selected input clock.
The Pre-Locked2 mode is a secondary, temporary mode.
3.10.2
T4 DPLL OPERATING MODE
The T4 path is simpler compared with the T0 path.
3.10.2.1
Free-Run Mode
In Free-Run mode, the T4 DPLL output refers to the master clock
and is affected by any input clock. The accuracy of the T4 DPLL output
is equal to that of the master clock.
3.10.2.2
Locked Mode
In Locked mode, the T4 selected input clock may be locked in the T4
DPLL.
When the T4 selected input clock is locked, the phase and frequency
offset of the T4 DPLL output track those of the T4 selected input clock;
when unlocked, the phase and frequency offset of the T4 DPLL output
attempt to track those of the selected input clock.
The T4 DPLL loop is closed in Locked mode. Its bandwidth and
damping factor are set by the T4_DPLL_LOCKED_BW[1:0] bits and the
T4_DPLL_LOCKED_DAMPING[2:0] bits respectively.
3.10.2.3
Holdover Mode
In Holdover mode, the T4 DPLL resorts to the stored frequency data
acquired in Locked mode to control its output. The T4 DPLL output is not
Table 19: Frequency Offset Control in Holdover Mode
MAN_HOLDOVER
AUTO_AVG
FAST_AVG
Frequency Offset Acquiring Method
0
don’t-care
Automatic Instantaneous
1
0
Automatic Slow Averaged
1
Automatic Fast Averaged
1
don’t-care
Manual
Table 20: Holdover Frequency Offset Read
READ_AVG FAST_AVG
Offset Value Read from
T0_HOLDOVER_FREQ[23:0]
0
don’t-care The value is equal to the one written to.
1
0
The value is acquired by Automatic Slow Averaged
method, not equal to the one written to.
1
The value is acquired by Automatic Fast Averaged
method, not equal to the one written to.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3280EQG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP |
| IDT82V3280EQGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PFG | 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1,500 系列:- 類型:時鐘緩沖器/驅(qū)動器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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