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參數(shù)資料
| 型號(hào)： | IDT82V3280EQG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 88/171頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC PLL WAN SE STRATUM 2 100TQFP |
| 標(biāo)準(zhǔn)包裝： | 90 |
| 類型： | 時(shí)鐘/頻率發(fā)生器，多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，PECL |
| 輸出： | CMOS，LVDS，PECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 14:9 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 622.08MHz |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-LQFP 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 100-TQFP-EP（14x14） |
| 包裝： | 托盤(pán) |
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IDT82V3280
WAN PLL
Functional Description
23
December 9, 2008
3.5
INPUT CLOCK QUALITY MONITORING
The qualities of all the input clocks are always monitored in the fol-
lowing aspects:
LOS (loss of signal) (only for IN1 and IN2)
Activity
Frequency
LOS monitoring is only conducted on IN1 and IN2. Activity and fre-
quency monitoring are conducted on all the input clocks.
The qualified clocks are available for T0/T4 DPLL selection. The T0
and T4 selected input clocks have to be monitored further. Refer to
Chapter 3.7 Selected Input Clock Monitoring for details.
3.5.1
LOS MONITORING
IN1 and IN2 support the AMI input signal. LOS monitoring is con-
ducted on IN1 and IN2. A LOS event occurs when the amplitude of the
input clock falls below +0.6 Vp-p for 1 ms; the LOS event is cleared
when the amplitude rises higher than +1 Vp-p.
LOS status is indicated by the AMI1_LOS 1 / AMI2_LOS 1 bit. If the
AMI1_LOS 2 / AMI2_LOS 2 bit is ‘1’, the occurrence of LOS will trigger
an interrupt.
The input clock in LOS status is disqualified for clock selection for T0/
T4 DPLL.
3.5.2
ACTIVITY MONITORING
Activity is monitored by using an internal leaky bucket accumulator,
as shown in Figure 4.
Each input clock is assigned an internal leaky bucket accumulator.
The input clock is monitored for each period of 128 ms and the internal
leaky bucket accumulator increases by 1 when an event is detected; it
decreases by 1 if no event is detected within the period set by the decay
rate. The event is that an input clock drifts outside (>) ±500 ppm with
respect to the master clock within a 128 ms period.
There are four configurations (0 - 3) for a leaky bucket accumulator.
The leaky bucket configuration for an input clock is selected by the cor-
responding BUCKET_SEL[1:0] bits. Each leaky bucket configuration
consists of four elements: upper threshold, lower threshold, bucket size
and decay rate.
The bucket size is the capability of the accumulator. If the number of
the accumulated events reach the bucket size, the accumulator will stop
increasing even if further events are detected. The upper threshold is a
point above which a no-activity alarm is raised. The lower threshold is a
point below which the no-activity alarm is cleared. The decay rate is a
certain period during which the accumulator decreases by 1 if no event
is detected.
The leaky bucket configuration is programmed by one of four groups
of register bits: the BUCKET_SIZE_n_DATA[7:0] bits, the UPPER_
THRESHOLD_n_DATA[7:0] bits,
the LOWER_THRESHOLD_n_
DATA[7:0] bits and the DECAY_RATE_n_DATA[1:0] bits respectively; ‘n’
is 0 ~ 3.
The no-activity alarm status of the input clock is indicated by the
INn_NO_ACTIVITY_ALARM bit (14
≥ n ≥ 1).
The input clock with a no-activity alarm is disqualified for clock selec-
tion for T0/T4 DPLL.
Figure 4. Input Clock Activity Monitoring
Input Clock
Leaky Bucket Accumulator
No-activity Alarm Indication
Decay
Rate
Bucket Size
Upper Threshold
Lower Threshold
0
clock signal with no event
clock signal with events
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| VE-B33-MW-F2 | CONVERTER MOD DC/DC 24V 100W |
| IDT82V3280PFG | IC PLL WAN SE STRATUM 2 100-TQFP |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT82V3280EQG8 | 制造商:Integrated Device Technology Inc 功能描述:IC PLL WAN SE STRATUM 2 100TQFP |
| IDT82V3280EQGBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PFBLANK | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:WAN PLL |
| IDT82V3280PFG | 功能描述:IC PLL WAN SE STRATUM 2 100-TQFP RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
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