參數(shù)資料
型號： IDT82V3280PFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 12/171頁
文件大?。?/td> 0K
描述： IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 14:9
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 82V3280PFG8
IDT82V3280
WAN PLL
Programming Information
109
December 9, 2008
IN_FREQ_READ_STS - Input Clock Frequency Read Value
IN1_IN2_STS - Input Clock 1 & 2 Status
Address: 42H
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 0
IN_FREQ_VALUE[7:0]
These bits represent a 2’s complement signed integer. If the value is multiplied by the value in the
FREQ_MON_FACTOR[3:0] bits (b3~0, 2EH), the frequency of an input clock with respect to the reference clock in ppm will
be gotten. The input clock is selected by the IN_FREQ_READ_CH[3:0] bits (b3~0, 41H).
The value in these bits is updated every 16 seconds, starting when an input clock is selected.
Address: 43H
Type: Read
Default Value: X110X110
Bit
Name
Description
7-
Reserved.
6
IN2_FREQ_HARD_ALARM
This bit indicates whether IN2 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
5
IN2_NO_ACTIVITY_ALARM
This bit indicates whether IN2 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
4
IN2_PH_LOCK_ALARM
This bit indicates whether IN2 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X
MULTI_FACTOR[1:0] (b7~6, 08H) in second
) which starts from when the alarm is raised.
3-
Reserved.
2
IN1_FREQ_HARD_ALARM
This bit indicates whether IN1 is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
1
IN1_NO_ACTIVITY_ALARM
This bit indicates whether IN1 is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
0
IN1_PH_LOCK_ALARM
This bit indicates whether IN1 is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0, 08H) X
MULTI_FACTOR[1:0] (b7~6, 08H) in second
) which starts from when the alarm is raised.
7
6543
210
IN_FREQ_VAL
UE7
IN_FREQ_VAL
UE6
IN_FREQ_VAL
UE5
IN_FREQ_VAL
UE4
IN_FREQ_VAL
UE3
IN_FREQ_VAL
UE2
IN_FREQ_VAL
UE1
IN_FREQ_VAL
UE0
7
6543
210
-
IN2_FREQ_HA
RD_ALARM
IN2_NO_ACTIV
ITY_ALARM
IN2_PH_LOCK
_ALARM
-
IN1_FREQ_HA
RD_ALARM
IN1_NO_ACTIV
ITY_ALARM
IN1_PH_LOCK
_ALARM
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參數(shù)描述
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