參數(shù)資料
型號: IDT82V3280PFG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 45/171頁
文件大?。?/td> 0K
描述: IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝: 750
類型: 時鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 14:9
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-LQFP
供應(yīng)商設(shè)備封裝: 100-TQFP(14x14)
包裝: 帶卷 (TR)
其它名稱: 82V3280PFG8
IDT82V3280
WAN PLL
Programming Information
139
December 9, 2008
OUT4_FREQ_CNFG - Output Clock 4 Frequency Configuration
Address: 6EH
Type: Read / Write
Default Value: 00000110
Bit
Name
Description
7 - 4
OUT4_PATH_SEL[3:0]
These bits select an input to OUT4.
0000 ~ 0011: The output of T0 APLL. (default: 0000)
0100: The output of T0 DPLL 77.76 MHz path.
0101: The output of T0 DPLL 12E1/24T1/E3/T3 path.
0110: The output of T0 DPLL 16E1/16T1 path.
0111: The output of T0 DPLL GSM/OBSAI/16E1/16T1 path.
1000 ~ 1011: The output of T4 APLL.
1100: The output of T4 DPLL 77.76 MHz path.
1101: The output of T4 DPLL 12E1/24T1/E3/T3 path.
1110: The output of T4 DPLL 16E1/16T1 path.
1111: The output of T4 DPLL GSM/GPS/16E1/16T1 path.
3 - 0
OUT4_DIVIDER[3:0]
These bits select a division factor of the divider for OUT4.
The output frequency is determined by the division factor and the signal derived from T0/T4 DPLL or T0/T4 APLL output
(selected by the OUT4_PATH_SEL[3:0] bits (b7~4, 6EH)). If the signal is derived from one of the T0/T4 DPLL outputs,
please refer to Table 24 for the division factor selection. If the signal is derived from the T0/T4 APLL output, please refer to
Table 25 for the division factor selection.
76543210
OUT4_PATH_S
EL3
OUT4_PATH_S
EL2
OUT4_PATH_S
EL1
OUT4_PATH_S
EL0
OUT4_DIVIDER
3
OUT4_DIVIDER
2
OUT4_DIVIDER
1
OUT4_DIVIDER
0
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