參數(shù)資料
型號： IDT82V3280PFG8
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 92/171頁
文件大?。?/td> 0K
描述： IC PLL WAN SE STRATUM 2 100-TQFP
標(biāo)準(zhǔn)包裝： 750
類型： 時鐘/頻率發(fā)生器，多路復(fù)用器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，PECL
輸出： CMOS，LVDS，PECL
電路數(shù)： 1
比率 - 輸入:輸出： 14:9
差分 - 輸入:輸出： 是/是
頻率 - 最大： 622.08MHz
電源電壓： 3 V ~ 3.6 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 100-LQFP
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 帶卷 (TR)
其它名稱： 82V3280PFG8
IDT82V3280
WAN PLL
Functional Description
27
December 9, 2008
3.7
SELECTED INPUT CLOCK MONITORING
The quality of the selected input clock is always monitored (refer to
Chapter 3.5 Input Clock Quality Monitoring) and the DPLL locking status
is always monitored.
3.7.1
T0 / T4 DPLL LOCKING DETECTION
The following events is always monitored:
Fast Loss;
Coarse Phase Loss;
Fine Phase Loss;
Hard Limit Exceeding.
3.7.1.1
Fast Loss
A fast loss is triggered when the selected input clock misses 2 con-
secutive clock cycles. It is cleared once an active clock edge is detected.
For T0 path, the occurrence of the fast loss will result in T0 DPLL
unlocked if the FAST_LOS_SW bit is ‘1’. For T4 path, the occurrence of
the fast loss will result in T4 DPLL unlocked regardless of the
FAST_LOS_SW bit.
3.7.1.2
Coarse Phase Loss
The T0/T4 DPLL compares the selected input clock with the feed-
back signal. If the phase-compared result exceeds the coarse phase
limit, a coarse phase loss is triggered. It is cleared once the phase-com-
pared result is within the coarse phase limit.
When the selected input clock is of 2 kHz, 4 kHz or 8 kHz, the coarse
phase limit depends on the MULTI_PH_8K_4K_2K_EN bit, the
WIDE_EN bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to
Table 10. When the selected input clock is of other frequencies but 2
kHz, 4 kHz and 8 kHz, the coarse phase limit depends on the WIDE_EN
bit and the PH_LOS_COARSE_LIMT[3:0] bits. Refer to Table 11.
The occurrence of the coarse phase loss will result in T0/T4 DPLL
unlocked if the COARSE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.3
Fine Phase Loss
The T0/T4 DPLL compares the selected input clock with the feed-
back signal. If the phase-compared result exceeds the fine phase limit
programmed by the PH_LOS_FINE_LIMT[2:0] bits, a fine phase loss is
triggered. It is cleared once the phase-compared result is within the fine
phase limit.
The occurrence of the fine phase loss will result in T0/T4 DPLL
unlocked if the FINE_PH_LOS_LIMT_EN bit is ‘1’.
3.7.1.4
Hard Limit Exceeding
Two limits are available for this monitoring. They are DPLL soft limit
and DPLL hard limit. When the frequency of the DPLL output with
respect to the master clock exceeds the DPLL soft / hard limit, a DPLL
soft / hard alarm will be raised; the alarm is cleared once the frequency
is within the corresponding limit. The occurrence of the DPLL soft alarm
does not affect the T0/T4 DPLL locking status. The DPLL soft alarm is
indicated by the corresponding T0_DPLL_SOFT_FREQ_ALARM /
T4_DPLL_SOFT_FREQ_ALARM bit. The occurrence of the DPLL hard
alarm will result in T0/T4 DPLL unlocked if the FREQ_LIMT_PH_LOS bit
is ‘1’.
The DPLL soft limit is set by the DPLL_FREQ_SOFT_LIMT[6:0] bits
and can be calculated as follows:
DPLL Soft Limit (ppm) = DPLL_FREQ_SOFT_LIMT[6:0] X 0.724
The DPLL hard limit is set by the DPLL_FREQ_HARD_LIMT[15:0]
bits and can be calculated as follows:
DPLL Hard Limit (ppm) = DPLL_FREQ_HARD_LIMT[15:0] X 0.0014
3.7.2
LOCKING STATUS
The DPLL locking status depends on the locking monitoring results.
The DPLL is in locked state if none of the following events is triggered
during 2 seconds; otherwise, the DPLL is unlocked.
Fast Loss (the FAST_LOS_SW bit is ‘1’);
Coarse Phase Loss (the COARSE_PH_LOS_LIMT_EN bit is
‘1’);
Fine Phase Loss (the FINE_PH_LOS_LIMT_EN bit is ‘1’);
DPLL Hard Alarm (the FREQ_LIMT_PH_LOS bit is ‘1’).
If the FAST_LOS_SW bit, the COARSE_PH_LOS_LIMT_EN bit, the
FINE_PH_LOS_LIMT_EN bit or the FREQ_LIMT_PH_LOS bit is ‘0’, the
DPLL locking status will not be affected even if the corresponding event
is triggered. If all these bits are ‘0’, the DPLL will be in locked state in 2
seconds.
The DPLL locking status is indicated by the T0_DPLL_LOCK /
T4_DPLL_LOCK bit.
The T4_STS 1 bit will be set when the locking status of the T4 DPLL
changes (from ‘lock’ to ‘unlock’ or from ‘unlock’ to ‘lock’). If the T4_STS 2
bit is ‘1’, an interrupt will be generated.
Table 10: Coarse Phase Limit Programming (the selected input
clock of 2 kHz, 4 kHz or 8 kHz)
MULTI_PH_8K_4K
_2K_EN
WIDE_EN
Coarse Phase Limit
0
don’t-care
±1 UI
1
0±1 UI
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
Table 11: Coarse Phase Limit Programming (the selected input
clock of other than 2 kHz, 4 kHz and 8 kHz)
WIDE_EN
Coarse Phase Limit
0±1 UI
1
set by the PH_LOS_COARSE_LIMT[3:0] bits
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