參數(shù)資料
型號(hào): IDT82V3355TFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 118/135頁
文件大?。?/td> 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 82V3355TFG
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
83
May 19, 2009
IN1_IN2_DIFF_STS - Differential Input Clock 1 & 2 Status
Address: 45H
Type: Read
Default Value: X110X110
Bit
Name
Description
7-
Reserved.
6
IN2_DIFF_FREQ_HARD_ALARM
This bit indicates whether IN2_DIFF is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
5
IN2_DIFF_NO_ACTIVITY_ALARM
This bit indicates whether IN2_DIFF is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
4
IN2_DIFF_PH_LOCK_ALARM
This bit indicates whether IN2_DIFF is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
3-
Reserved.
2
IN1_DIFF_FREQ_HARD_ALARM
This bit indicates whether IN1_DIFF is in frequency hard alarm status.
0: No frequency hard alarm.
1: In frequency hard alarm status. (default)
1
IN1_DIFF_NO_ACTIVITY_ALARM
This bit indicates whether IN1_DIFF is in no-activity alarm status.
0: No no-activity alarm.
1: In no-activity alarm status. (default)
0
IN1_DIFF_PH_LOCK_ALARM
This bit indicates whether IN1_DIFF is in phase lock alarm status.
0: No phase lock alarm. (default)
1: In phase lock alarm status.
If the PH_ALARM_TIMEOUT bit (b5, 09H) is ‘0’, this bit is cleared by writing ‘1’ to this bit; if the
PH_ALARM_TIMEOUT bit (b5, 09H) is ‘1’, this bit is cleared after a period (= TIME_OUT_VALUE[5:0] (b5~0,
08H) X MULTI_FACTOR[1:0] (b7~6, 08H) in second) which starts from when the alarm is raised.
7
654
3
210
-
IN2_DIFF_FREQ
_HARD_ALARM
IN2_DIFF_NO_A
CTIVITY_ALARM
IN2_DIFF_PH_L
OCK_ALARM
-
IN1_DIFF_FREQ
_HARD_ALARM
IN1_DIFF_NO_A
CTIVITY_ALARM
IN1_DIFF_PH_L
OCK_ALARM
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