參數資料
型號: IDT82V3355TFG
廠商: IDT, Integrated Device Technology Inc
文件頁數: 78/135頁
文件大小: 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
標準包裝: 1
類型: 時鐘/頻率發(fā)生器,多路復用器
PLL:
主要目的: 以太網,SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數: 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 82V3355TFG
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
47
May 19, 2009
6
PROGRAMMING INFORMATION
After reset, all the registers are set to their default values. The regis-
ters are read or written via the microprocessor interface.
Before
any
write
operation,
the
value
in
register
PROTECTION_CNFG is recommended to be confirmed to make sure
whether the write operation is enabled. The device provides 3 register
protection modes:
Protected mode: no other registers can be written except register
PROTECTION_CNFG itself;
Fully Unprotected mode: all the writable registers can be written;
Single Unprotected mode: one more register can be written
besides register PROTECTION_CNFG. After write operation
(not including writing a ‘1’ to clear a bit to ‘0’), the device auto-
matically switches to Protected mode.
Writing ‘0’ to the registers will take no effect if the registers are
cleared by writing ‘1’.
T0 and T4 paths share some registers, whose addresses are 27H,
28H, 2AH, 4EH, 4FH, 5AH, 5BH, 62H ~ 64H, 68H and 69H. The names
of shared registers are marked with a *. Before register read/write oper-
ation, register T4_T0_REG_SEL_CNFG is recommended to be con-
firmed to make sure whether the register operation is available for T0 or
T4 path.
The access of the Multi-word Registers is different from that of the
Single-word Registers. Take the registers (04H, 05H and 06H) for an
example, the write operation for the Multi-word Registers follows a fixed
sequence. The register (04H) is configured first and the register (06H) is
configured last. The three registers are configured continuously and
should not be interrupted by any operation. The crystal calibration con-
figuration will take effect after all the three registers are configured. Dur-
ing read operation, the register (04H) is read first and the register (06H)
is read last. The crystal calibration reading should be continuous and not
be interrupted by any operation.
Certain bit locations within the device register map are designated as
Reserved. To ensure proper and predictable operation, bits designated
as Reserved should not be written by the users. In addition, their value
should be masked out from any testing or error detection methods that
are implemented.
6.1
REGISTER MAP
Table 35 is the map of all the registers, sorted in an ascending order
of their addresses.
Table 35: Register List and Map
Address
(Hex)
Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reference
Page
Global Control Registers
00
ID[7:0] - Device ID 1
ID[7:0]
01
ID[15:8] - Device ID 2
ID[15:8]
04
NOMINAL_FREQ_VALUE[7:0]
05
NOMINAL_FREQ_VALUE[15:8]
06
NOMINAL_FREQ_VALUE[23:16]
07
---
T4_T0_SE
L
---
-
08
MULTI_FACTOR[1:0]
TIME_OUT_VALUE[5:0]
09
AUTO_EX
T_SYNC_
EN
EXT_SYN
C_EN
PH_ALAR
M_TIMEO
UT
SYNC_FREQ[1:0]
IN_SONET
_SDH
-
REVERTIV
E_MODE
0A
---
--
OSC_EDG
E
OUT1_PE
CL_LVDS
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