參數(shù)資料
型號(hào): IDT82V3355TFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/135頁
文件大?。?/td> 0K
描述: IC PLL WAN SYNC ETH 64-TQFP
標(biāo)準(zhǔn)包裝: 1
類型: 時(shí)鐘/頻率發(fā)生器,多路復(fù)用器
PLL:
主要目的: 以太網(wǎng),SONET/SDH,Stratum
輸入: CMOS,LVDS,PECL
輸出: CMOS,LVDS,PECL
電路數(shù): 1
比率 - 輸入:輸出: 3:2
差分 - 輸入:輸出: 是/是
頻率 - 最大: 622.08MHz
電源電壓: 3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-TQFP(10x10)
包裝: 托盤
其它名稱: 82V3355TFG
IDT82V3355
SYNCHRONOUS ETHERNET WAN PLL
Programming Information
102
May 19, 2009
DPLL_FREQ_HARD_LIMIT[15:8]_CNFG - DPLL Hard Limit Configuration 2
CURRENT_DPLL_PHASE[7:0]_STS - DPLL Current Phase Status 1 *
CURRENT_DPLL_PHASE[15:8]_STS - DPLL Current Phase Status 2 *
Address: 67H
Type: Read / Write
Default Value: 00011001
Bit
Name
Description
7 - 0
DPLL_FREQ_HARD_LIMT[15:8]
The DPLL_FREQ_HARD_LIMT[15:0] bits represent an unsigned integer. If the value is multiplied by 0.0014, the
DPLL hard limit for T0 and T4 paths in ppm will be gotten.
The DPLL hard limit is symmetrical about zero.
Address: 68H
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 0
CURRENT_PH_DATA[7:0] Refer to the description of the CURRENT_PH_DATA[15:8] bits (b7~0, 69H).
Address: 69H
Type: Read
Default Value: 00000000
Bit
Name
Description
7 - 0
CURRENT_PH_DATA[15:8]
The CURRENT_PH_DATA[15:0] bits represent a 2’s complement signed integer. If the value is multiplied by 0.61, the
averaged phase error of the T0/T4 DPLL feedback with respect to the selected input clock in ns will be gotten.
765
4
3
2
1
0
DPLL_FREQ_H
ARD_LIMT15
DPLL_FREQ_H
ARD_LIMT14
DPLL_FREQ_H
ARD_LIMT13
DPLL_FREQ_H
ARD_LIMT12
DPLL_FREQ_H
ARD_LIMT11
DPLL_FREQ_H
ARD_LIMT10
DPLL_FREQ_H
ARD_LIMT9
DPLL_FREQ_H
ARD_LIMT8
76543210
CURRENT_PH
_DATA7
CURRENT_PH
_DATA6
CURRENT_PH
_DATA5
CURRENT_PH
_DATA4
CURRENT_PH
_DATA3
CURRENT_PH
_DATA2
CURRENT_PH
_DATA1
CURRENT_PH
_DATA0
76543210
CURRENT_PH
_DATA15
CURRENT_PH
_DATA14
CURRENT_PH
_DATA13
CURRENT_PH
_DATA12
CURRENT_PH
_DATA11
CURRENT_PH
_DATA10
CURRENT_PH
_DATA9
CURRENT_PH
_DATA8
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