參數(shù)資料
型號(hào)： IDT88P8341BHI
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 67/96頁
文件大小： 0K
描述： IC SPI3-SPI4 EXCHANGE 820-PBGA
標(biāo)準(zhǔn)包裝： 24
系列： *
其它名稱： 88P8341BHI
7
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
List of Tables (Continued)
Table 112 - SPI-4 ingress bit alignment counter register (0x02 to 0x0B) ......................................................................................................................... 73
Table 113 - SPI-4 ingress manual alignment phase/result register (0x0C to 0x1F) .......................................................................................................... 73
Table 114 - SPI -4 egress data lane timing register (register_offset 0x2A) ....................................................................................................................... 73
Table 115 - SPI-4 egress Control Lane Timing register (Register_offset 0x2B) ............................................................................................................... 74
Table 116 - SPI-4 egress data clock timing register (register_offset 0x2C) ....................................................................................................................... 74
Table 117 - SPI-4 egress status timing register (register_offset 0x2D) ............................................................................................................................ 74
Table 118 - SPI-4 egress status clock timing register (register_offset 0x2E) .................................................................................................................... 74
Table 119 - PMON timebase control register (register_offset 0x00) ................................................................................................................................. 75
Table 120 - Timebase register (register_offset 0x01) ...................................................................................................................................................... 75
Table 121 - Clock generator control register (register_offset 0x10) ................................................................................................................................. 75
Table 122 - OCLK and MCLK frequency select encoding ............................................................................................................................................... 75
Table 123 - GPIO register (register_offset 0x20) ............................................................................................................................................................ 76
Table 124 - GPIO monitor table (5 entries 0x21-0x25 for GPIO[0] through GPIO[4]) ....................................................................................................... 76
Table 125 - Version number register (register_offset 0x30) ............................................................................................................................................. 76
Table 126 – JTAG instructions ........................................................................................................................................................................................ 77
Table 127 – Absolute maximum ratings ........................................................................................................................................................................... 77
Table 128 – Recommended Operating Conditions .......................................................................................................................................................... 77
Table 129 – Terminal Capacitance ................................................................................................................................................................................. 78
Table 130 – Thermal Characteristics .............................................................................................................................................................................. 78
Table 131 – DC Electrical characteristics ........................................................................................................................................................................ 79
Table 132 – SPI-3 AC Input / Output timing specifications ................................................................................................................................................ 80
Table 133 – SPI-4.2 LVDS AC Input / Output timing specifications .................................................................................................................................... 82
Table 134 – SPI-4 LVTTL status AC Characteristics ....................................................................................................................................................... 82
Table 135 – REF_CLK clock input ................................................................................................................................................................................. 82
Table 136 – OCLK[3:0] clock inputs and MCLK internal clock ......................................................................................................................................... 82
Table 137 – Microprocessor interface ............................................................................................................................................................................ 82
Table 138 – Microprocessor parallel port Motorola read timing ....................................................................................................................................... 83
Table 139 – Microprocessor parallel port Motorola write timing ....................................................................................................................................... 84
Table 140 – Microprocessor parallel port Intel mode read timing ..................................................................................................................................... 85
Table 141 – Microprocessor parallel port Intel mode write timing ..................................................................................................................................... 86
Table 142 – Microprocessor serial peripheral interface timing ......................................................................................................................................... 87
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參數(shù)描述
IDT88P8342BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8342BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:SPI EXCHANGE 4 x SPI-3 TO SPI-4 Issue 1.0
IDT88P8344BHGI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:是 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
IDT88P8344BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA（27x27） 包裝:散裝
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