參數(shù)資料
型號: IDT88P8341BHI
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 9/96頁
文件大?。?/td> 0K
描述: IC SPI3-SPI4 EXCHANGE 820-PBGA
標準包裝: 24
系列: *
其它名稱: 88P8341BHI
17
IDT88P8341 SPI EXCHANGE SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
3.2 SPI-4
Refer to OIF SPI-4 document (see Glossary) for full details of the implemen-
tationagreement.
- Clock rate is 80 - 400 MHz (160 - 800MHz DDR)
- Link and PHY modes supported
- Address range 0 to 255 with support for 64 simultaneously active logical
ports
- MAXBURST parameters configurable 16-256 bytes in 16 byte multiples
- 256 entry calendar
- LVTTL and LVDS status signals supported
The following are implemented for the SPI-4 interface:
- Link / PHY layer device
- Physical port active
3.2.1 SPI-4 ingress
The SPI-4 ingress includes
Bit alignment
Wordalignment/de-skew
Transfer decode and dispatch
PFPinterface
Statusframegeneration
SPI-4 ingress configurable parameters
SPI-4 LID map
- 256 entries, one per SPI-4 LP
- SPI-3 physical interface identifier
- Physical port enable
Word / bit synchronization
- LVDS clock data alignment and LVDS data de-skew
Minimum packet length
- Packets shorter than the minimum length will be optionally counted in the
short packet counter.
- Range 0 – 255 in 1 byte increments
Maximum packet length
- Packets longer than the maximum length will be optionally counted in the
long packet counter.
- Range 0 – 16,383 in 1 byte increments
Free segment backpressure threshold
-NumberoffreebuffersegmentsallocatedtotriggerbackpressurefortheLP
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IDT88P8344BHI 功能描述:IC SPI3-SPI4 EXCHANGE 820-PBGA RoHS:否 類別:集成電路 (IC) >> 專用 IC 系列:* 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1 系列:- 類型:調(diào)幀器 應(yīng)用:數(shù)據(jù)傳輸 安裝類型:表面貼裝 封裝/外殼:400-BBGA 供應(yīng)商設(shè)備封裝:400-PBGA(27x27) 包裝:散裝