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| 型號： | IDT88P8344BHI |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 49/98頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC SPI3-SPI4 EXCHANGE 820-PBGA |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | * |
| 其它名稱： | 88P8344BHI |
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53
IDT88P8344 SPI EXCHANGE 4 x SPI-3 TO SPI-4
INDUSTRIALTEMPERATURERANGE
APRIL 10, 2006
I_SYNCH_EN
SPI-4 ingress data path has transitioned from out of
synchronization to in synchronization condition interrupt indication enable.
0=Disable synchronization interrupt
1=Enable synchronization interrupt
I_BUS_ERR_EN
SPI-4 ingress bus error interrupt indication enable.
0=Disable bus error interrupt
1=Enable bus error interrupt
SPI4_INACTIVE_TRANSFER_EN SPI-4ingressinactivetransferinter-
rupt indication enable.
0=Disable inactive transfer interrupt
1=Enable inactive transfer interrupt
DCLK_UN_EN SPI-4 ingress data clock has transitioned from available
to an unavailable condition interrupt indication enable.
0=Disable unavailable interrupt
1=Enable unavailable interrupt
E_DIP_ERR_EN
SPI-4 egress DIP-2 error interrupt indication enable
on the SPI-4 egress status channel.
0=Disable DIP-2 error interrupt
1=Enable DIP-2 error interrupt
E_SYNCH_EN SPI-4 egress status channel has transitioned from out of
synchronization to in synchronization condition interrupt indication enable.
0=Disable synchronization interrupt
1=Enable synchronization interrupt
SCLK_UN_EN SPI-4egressstatusclockhastransitionedfromavailable
to an unavailable condition interrupt indication enable. SCLK_UN_EN should
be written as a zero if using a SPI-4 egress LVTTL status clock that is less than
one-half of the MCLK frequency. The SCLK_UN_I interrupt indication is not
usable in this case.
0=Disable unavailable interrupt
1=Enable unavailable interrupt
Module status register (0x24 to 0x27 in the direct
accessed space)
Field
Bits
Length
Initial Value
SPI-34_CAPTURE
0
1
0
SPI-43_CAPTURE
1
0
SPI-34_INSERT
2
1
0
SPI-43_INSERT
3
1
0
PMON
4
1
0
Reserved
7:5
3
0
TABLE 42 - MODULE STATUS REGISTER (0x24 TO
0x27 IN THE DIRECT ACCESSED SPACE)
The Module Status registers (0x24 to 0x27 in the direct accessed space)
have read and write access, and interrupt status fields are cleared by a
microprocessor write cycle, where a logical one must be written to clear the
field(s) targeted, except for the PMON field, which can not be cleared.
TheModuleStatusregistersaresecondaryinterruptstatusregistersandcan
only be active if the corresponding field is active in the Primary Interrupt Status
Register (Direct 0x2C):
Module Status Register 0x24 is for module A, and can only be active if the
MODULE_A field is active in the Primary Interrupt Status Register.
Module Status Register 0x25 is for module B, and can only be active if the
MODULE_B field is active in the Primary Interrupt Status Register.
Module Status Register 0x26 is for module C, and can only be active if the
MODULE_C field is active in the Primary Interrupt Status Register.
Module Status Register 0x27 is for module D, and can only be active if the
MODULE_D field is active in the Primary Interrupt Status Register.
SPI-34_CAPTURE
SPI-3 ingress to SPI-4 egress capture event inter-
ruptindication.
0=No capture event
1=Buffer is ready for reading by the microprocessor
SPI-43_CAPTURE
SPI-4ingresstoSPI-3egresscaptureeventinterrupt
indication.
0=No capture event
1=Buffer is ready for reading by the microprocessor
SPI-34_INSERT SPI-3 ingress to SPI-4 egress insert event interrupt
indication.
0=No insert event
1=Buffer is ready for writing by the microprocessor
SPI-43_INSERT
SPI-4 ingress to SPI-3 egress insert event interrupt
indication.
0=No insert event
1=Buffer is ready for writing by the microprocessor
PMON PerformanceMonitoreventinterruptindication.Writingtothisfieldhas
noeffect.
0=No PMON event
1=PMON event is ready for reading by the microprocessor
Module enable register (0x28 to 0x2B in the direct
accessed space)
The Module Enable registers (0x28 to 0x2B in the direct accessed space)
have read and write access.
Module Enable Register 0x28 is for module A.
Module Enable Register 0x29 is for module B.
Module Enable Register 0x2A is for module C.
Module Enable Register 0x2B is for module D.
Field
Bits
Length
Initial Value
SPI-34 CAPTURE_EN
0
1
0
SPI-43 CAPTURE_EN
1
0
SPI-34 INSERT_EN
2
1
0
SPI-43 INSERT_EN
3
1
0
PMON_EN
4
1
0
Reserved
7:5
3
0
TABLE 43 - MODULE ENABLE REGISTER (0x28 TO
0x2B IN THE DIRECT ACCESSED SPACE)
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